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Programmable Low Overhead, Run Length Limited and DC-Balanced Line Coding for High-Speed Serial Data Transmission

Abstract : Thanks to their routing simplicity, noise, EMI (Electro-Magnetic Interferences), area and power consumption reduction advantages over parallel links, High Speed Serial Links (HSSLs) are found in almost all today's System-on-Chip (SoC) connecting different components: the main chip to its Inputs/Outputs (I/Os), the main chip to a companion chip, Inter-Processor Communication (IPC) and etc… Serial memory might even be the successor of current DDR memories.However, going from parallel links to high-speed serial links presents many challenges; HSSLs must run at higher speeds reaching many gigabits per second to maintain the same end-to-end throughput as parallel links as well as satisfying the exponential increase in the demand for throughput. The signal's attenuation over copper increases with the frequency, requiring more equalizers and filtering techniques, thereby increasing the design complexity and the power consumption.One way to optimize the design at high speeds is to embed the clock within the data, because a clock line means more routing surface, and it also can be source to high EMI. Another good reason to use an embedded clock is that the skew (time mismatch between the clock and the data lanes) becomes hard to control at high frequencies. Transitions must then be ensured inside the data that is sent on the line, for the receiver to be able to synchronize and recover the data correctly. In other words, the number of Consecutive Identical Bits (CIBs) also called the Run Length (RL) must be reduced or bounded to a certain limit.Another challenge and characteristic that must be bounded or reduced in the data to send on a HSSL is the difference between the number of ‘0' bits and ‘1' bits. It is called the Running Disparity (RD). Big differences between 1's and 0's could shift the signal from the reference line. This phenomenon is known as Base-Line Wander (BLW) that could increase the BER (Bit Error Rate) and require filtering or equalizing techniques to be corrected at the receiver, increasing its complexity and power consumption.In order to ensure a bounded Run Length and Running Disparity, the data to be transmitted is generally encoded. The encoding procedure is also called line coding. Over time, many encoding methods were presented and used in the standards; some present very good characteristics but at the cost of high additional bits, also called bandwidth overhead, others have low or no overhead but do not ensure the same RL and RD bounds, thus requiring more analog design complexity and increasing the power consumption.In this thesis, we propose a novel programmable line coding that can perform to the desired RL and RD bounds with a very low overhead, down to 10 times lower that the existing used encodings and for the same bounds. First, we show how we can obtain a very low overhead RL limited line coding, and second we propose a very low overhead method which bounds the RD, and then we show how we can combine both techniques in order to build a low overhead, Run Length Limited, and Running Disparity bounded Line Coding
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Submitted on : Tuesday, January 9, 2018 - 5:50:58 PM
Last modification on : Wednesday, July 22, 2020 - 3:01:19 AM
Long-term archiving on: : Friday, May 4, 2018 - 4:25:48 PM


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  • HAL Id : tel-01679262, version 1




Julien Saade. Programmable Low Overhead, Run Length Limited and DC-Balanced Line Coding for High-Speed Serial Data Transmission. Networking and Internet Architecture [cs.NI]. Université Grenoble Alpes, 2015. English. ⟨NNT : 2015GREAM079⟩. ⟨tel-01679262⟩



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