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Méthodologie de conception d’architectures reconfigurables dynamiquement pour des applications temps-réel

Abstract : Despite promising capabilities, FPGAs partial reconfiguration feature is not anchored in the industry yet, mostly for two reasons. First of all, Xilinx controller shows low performance and might introduce a large time overhead compared to the task period, incompatible with the use of partial reconfiguration. Also, developing such a dynamic application requires an extra design effort compared to a static solution for developing scheduling strategies. Indeed, it is impossible to evaluate an architecture and/or a scheduling algorithm to verify that real-time constraints are met before the implementation step. This thesis offers solutions to the issues previously mentioned. We will first introduce FaRM, a Fast Reconfiguration Manager reaching partial reconfiguration theoretical limits thanks to an efficient compression algorithm and an optimised architecture. Then, we present RecoSim, a high-level SystemC simulator for reconfigurable architectures. It makes use of FaRM reconfiguration overhead cost model to allow for developing and verifying scheduling algorithms. Finally, we will show how these contributions are used inside FoRTReSS, a Flow for Reconfigurable archiTectures in Real-time SystemS compliant with Xilinx partial reconfiguration design flow. This work was carried out in the framework of project ARDMAHN, sponsored by the French National Research Agency.
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Contributor : François Duhem Connect in order to contact the contributor
Submitted on : Thursday, August 10, 2017 - 9:51:43 PM
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  • HAL Id : tel-01573906, version 1



François Duhem. Méthodologie de conception d’architectures reconfigurables dynamiquement pour des applications temps-réel. Systèmes embarqués. Univ. Nice-Sophia Antipolis, 2012. Français. ⟨tel-01573906⟩



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