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Automatic synthesis of hardware accelerator from high-level specifications of physical layers for flexible radio

Abstract : The Internet of Things (IoT) aims at connecting billions of communicating devices through an internet-like network. To this aim, the access to these things is expected to be performed via wireless technologies without using any predefined infrastructures or standards. This technology requires defining and implementing smart nodes capable to adapt to different radio communication protocols. In this thesis, we have defined a design methodology/flow, for such smart nodes, starting from their high-level specification down to their implementation in FPGA fabrics. This flow aims at improving the programmability of the waveforms by leveraging some high-level specifications. Thus, it relies on the High-Level Synthesis (HLS) for rapid prototyping of the waveforms functional blocks as well as the dataflow model of computation. Its entry point is Domain-Specific Language which enables modeling a waveform while inserting some implementation constraints for reconfigurable architectures such as the FPGAs. The flow is featured with a compiler which purpose is to produce some synthesis scripts and generate some RTL source code. The final waveform consists of a datapath and a control unit implemented as a Hierarchical Finite State Machine (HFSM).
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https://tel.archives-ouvertes.fr/tel-01492963
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Submitted on : Monday, March 20, 2017 - 4:53:01 PM
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OUEDRAOGO_Stephane.pdf
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  • HAL Id : tel-01492963, version 1

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Ganda Stéphane Ouedraogo. Automatic synthesis of hardware accelerator from high-level specifications of physical layers for flexible radio. Networking and Internet Architecture [cs.NI]. Université Rennes 1, 2014. English. ⟨NNT : 2014REN1S183⟩. ⟨tel-01492963⟩

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