. Fpga-en-utilisant-l-'interface and . Simulink, Pour ce faire, nous générons le bitstream du code VHDL synthétisable du système global Ce fichier est implémenté sur la cible FPGA et ensuite illustré par un bloc FIL s'insérant dans le modèle SIMULINK. Il s'agit alors d'une co-simulation entre la partie software (modèle SIMULINK et solveur associé

?. Figure, 16 : Résultats de simulation du modèle global en (en noir) virgule flottante sous modèle SIMULINK et (en magenta) son équivalent implémenté sur la cible FPGA

. Dans-ce-chapitre, étage de reconstruction numérique Nous avons fait un travail d'adéquation algorithme-architecture à l'aide de deux flots de conception : l'un dépendant de la cible FPGA (SysGen pour Xilinx), l'autre indépendant de la cible choisie puisqu'il permet la génération d'une description VHDL standard pouvant être utilisée sur n'importe quelle cible. L'optimisation de l'architecture s'est effectuée selon la contrainte surface pour être sûr de pouvoir utiliser la cible à notre disposition. Cela s'est traduit par un rallongement du chemin critique, mais toujours dans les spécifications requises, Il sera intéressant de poursuivre ce travail de façon analytique en proposant une méthode pour optimiser le codage de la virgule fixe sur un nombre de bits plus faible et surtout d'envisager des architectures avec des chemins critiques plus courts

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