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Compensation numérique pour convertisseur large bande hautement parallélisé.

Abstract : Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.
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Submitted on : Tuesday, June 14, 2016 - 9:12:07 AM
Last modification on : Tuesday, January 19, 2021 - 3:16:17 AM
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  • HAL Id : tel-01331558, version 1


Nicolas Le Dortz. Compensation numérique pour convertisseur large bande hautement parallélisé.. Autre. CentraleSupélec, 2015. Français. ⟨NNT : 2015CSUP0002⟩. ⟨tel-01331558⟩



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