Preesm peut être étendu afin de devenir un ensemble permettant l'ordonnancement statique, quasi-statique et dynamique d'applications flux de données. Il peut ainsi fournir de précieux indicateurs de prototypage rapide aux concepteurs d ,
103 7.10 Overall Execution Time vs N value in homogeneous pattern ,
128 A.2 Ordonnancement Multiprocesseur d'une application sur une plateforme composée de deux processeurs, p.129 ,
Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), pp.123-129, 2013. ,
DOI : 10.1109/AHS.2013.6604235
URL : https://hal.archives-ouvertes.fr/hal-00877643
An experimental toolchain based on high-level dataflow models of computation for heterogeneous mpsoc, DASIP, p.page xx, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00749175
Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.36-40, 2014. ,
DOI : 10.1109/EDERC.2014.6924354
URL : https://hal.archives-ouvertes.fr/hal-01059313
Dataflow-based adaptive multicore execution on a xilinx zynq platform, DATE Conference University booth, p.86, 2013. ,
Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.167-171, 2014. ,
DOI : 10.1109/EDERC.2014.6924381
URL : https://hal.archives-ouvertes.fr/hal-01067052
Just-in-time scheduling techniques for multicore signal processing systems, Signal and Information Processing (GlobalSIP), 2014 IEEE Global Conference on, pp.25-29, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01101790
Demonstrating a dataflowbased rtos for heterogeneous mpsoc by means of a stereo matching application, DASIP, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01101788
Pisdf: Parameterized & interfaced synchronous dataflow for mpsocs runtime reconfiguration, 1st Workshop on MEthods and TOols for Dataflow PrOgramming (METODO), 2014. Bibliography [66A13] 66ak2h12 -Multicore DSP+ARM KeyStone II System-on-Chip (SoC), pp.2015-2022 ,
URL : https://hal.archives-ouvertes.fr/hal-01075114
Improving performance and productivity for software development on TI Multicore DSP platforms, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.31-35, 2014. ,
DOI : 10.1109/EDERC.2014.6924353
FFTs in external of hierarchical memory, Proceedings of the 1989 ACM/IEEE conference on Supercomputing, pp.234-242, 1989. ,
The lambda calculus, p.22, 1984. ,
Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001. ,
DOI : 10.1109/78.950795
Low-overhead runtime scheduling for fine-grained acceleration of signal processing systems, Signal Processing Systems, pp.457-462, 2007. ,
Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996. ,
DOI : 10.1109/78.485935
P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.983-987, 2012. ,
DOI : 10.1109/DATE.2012.6176639
Ptolemy: A framework for simulating and prototyping heterogeneous systems, p.18, 1994. ,
Optimization of signal processing software for control system implementation, IEEE International Conference on Control Applications IEEE International Symposium on Intelligent Control, pp.1562-1567, 2006. ,
Scheduling dynamic dataflow graphs with bounded memory using the token flow model ICASSP-93 A Grimm collection of MIMD fairy tales, Acoustics, Speech, and Signal Processing IEEE International Conference on Frontiers of Massively Parallel Computation Fourth Symposium on the, pp.429-432, 1992. ,
Quasi-static scheduling for fine-grained embedded multiprocessing, p.70, 2009. ,
Minimizing synchronization overhead in statically scheduled multiprocessor systems, Application Specific Array Processors Proceedings. International Conference on, pp.298-309, 1995. ,
Affine Data-Flow Graphs for the Synthesis of Hard Real-Time Applications, 2012 12th International Conference on Application of Concurrency to System Design, pp.183-192, 2012. ,
DOI : 10.1109/ACSD.2012.16
URL : https://hal.archives-ouvertes.fr/hal-00763387
Static scheduling and code generation from dynamic dataflow graphs with integer-valued control streams, Signals, Systems and Computers Conference Record of the Twenty-Eighth Asilomar Conference on, pp.508-513, 1994. ,
Parallel FFT algorithms on network-on-chips, Information Technology: New Generations Fifth International Conference on, pp.1087-1093, 2008. ,
An algorithm for the machine calculation of complex fourier series, Mathematics of computation, vol.19, issue.90, pp.297-301, 1965. ,
Petri Nets and Grafcet: Tools for Modelling Discrete Event Systems 21 [dD13] Benoit Dupont de Dinechin. Dataflow language compilation for a single chip massively parallel processor, 2013 IEEE 6th International Workshop on Multi-/Many-core Computing Systems (MuCoCoS), pp.1-1, 1992. ,
Pisdf: Parameterized & interfaced synchronous dataflow for mpsocs runtime reconfiguration, 1st Workshop on MEthods and TOols for Dataflow PrOgramming (METODO), 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01075114
PiMM: Parameterized and Interfaced Dataflow Meta- Model for MPSoCs Runtime Reconfiguration, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on, pp.41-48 ,
Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications, 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1111-1115, 2015. ,
DOI : 10.1109/ICASSP.2015.7178142
URL : https://hal.archives-ouvertes.fr/hal-01146340
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs, Journal of Signal Processing Systems, vol.23, issue.1, pp.19-37, 2015. ,
DOI : 10.1007/s11265-014-0952-6
URL : https://hal.archives-ouvertes.fr/hal-01083576
CAL language report: Specification of the CAL actor language, p.23, 2003. ,
Chiron: A multi-paradigm logic. From Insight to Proof: Festschrift in Honour of Andrzej Trybulec Spdf: A schedulable parametric data-flow moc, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp.1-19, 2007. ,
Some computer organizations and their effectiveness. Computers, IEEE Transactions on, vol.100, issue.9, pp.948-960, 1972. ,
Sequencing and scheduling: an introduction to the mathematics of the job-shop, Ellis Horwood Chichester, vol.683, p.72, 1982. ,
Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), pp.123-129, 2013. ,
DOI : 10.1109/AHS.2013.6604235
URL : https://hal.archives-ouvertes.fr/hal-00877643
An experimental toolchain based on high-level dataflow models of computation for heterogeneous mpsoc, DASIP, page xx, 2012. ,
Embedded Systems Design, Newnes, 2002. ,
Demonstrating a dataflowbased rtos for heterogeneous mpsoc by means of a stereo matching application, DASIP, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01101788
Dataflow-based adaptive multicore execution on a xilinx zynq platform, DATE Conference University booth, p.86, 2013. ,
Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.167-171, 2014. ,
DOI : 10.1109/EDERC.2014.6924381
URL : https://hal.archives-ouvertes.fr/hal-01067052
Just-in-time scheduling techniques for multicore signal processing systems, 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP), pp.25-29, 2014. ,
DOI : 10.1109/GlobalSIP.2014.7032071
URL : https://hal.archives-ouvertes.fr/hal-01101790
Trends in multicore dsp platforms, Signal Processing Magazine IEEE, issue.6, pp.2638-2687, 2009. ,
The semantics of a simple language for parallel programming Programmability with flexibility: Autonomous single instruction multiple data systems Systolic arrays (for VLSI), Information Processing'74: Proceedings of the IFIP Congress, pp.471-475, 1974. ,
Mapping parameterized cyclo-static dataflow graphs onto configurable hardware High-performance Algorithms of Compile-time Scheduling of Parallel Processors (People's Republic of China MPSoC programming using the MAPS compiler, 1997. AAI9820493. 40 [LC10] Rainer Leupers and Jeronimo Castrillon Design Automation Conference 15th Asia and South Pacific, pp.285-301, 2005. ,
Scheduling strategies for multiprocessor real-time DSP, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond, pp.1279-1283, 1989. ,
DOI : 10.1109/GLOCOM.1989.64160
Static Scheduling of Synchronous Data Flow onto Multiprocessors for Embedded DSP Systems Synchronous data flow, Third International Conference on Measuring Technology and Mechatronics Automation (ICMTMA) Proceedings of the IEEE Dataflow process networks. Proceedings of the IEEE, pp.338-341, 1987. ,
Executable UML: A foundation for model-driven architectures 21 [meg] Megahertz myth | Technology | The Guardian, pp.2015-2024, 2002. ,
Open event machine: A multi-core run-time designed for performance, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.41-45, 2014. ,
DOI : 10.1109/EDERC.2014.6924355
Cramming more components onto integrated circuits, p.126, 1965. ,
Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP, Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, p.113, 2014. ,
DOI : 10.1109/DASIP.2014.7115636
URL : https://hal.archives-ouvertes.fr/hal-01101822
Accessed: 2015-09-21 On building an accurate stereo matching system on graphics hardware, Computer Vision Workshops (ICCV Workshops) IEEE International Conference on, pp.134-467, 2011. ,
Mapping of applications to MPSoCs Hierarchical reconfiguration of dataflow models, Proceedings of the seventh IEEE Formal Methods and Models for Co-Design MEM- OCODE'04. Proceedings. Second ACM and IEEE International Conference on, pp.109-118, 2004. ,
Physical layer multi-core prototyping: a dataflow-based approach for LTE eNodeB, p.74, 2012. ,
DOI : 10.1007/978-1-4471-4210-2
URL : https://hal.archives-ouvertes.fr/hal-00739957
A hierarchical multiprocessor scheduling framework for synchronous dataflow graphs Electronics Research Laboratory, College of Engineering, University of California Interface-based hierarchy for synchronous data-flow graphs, Signal Processing Systems, pp.65-74, 1995. ,
Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.36-40, 2014. ,
DOI : 10.1109/EDERC.2014.6924354
URL : https://hal.archives-ouvertes.fr/hal-01059313
Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer Mapped onto Multi-Core DSPs. phdthesis, p.48, 2010. ,
URL : https://hal.archives-ouvertes.fr/tel-00578043
Data Flow modeling and multi-core optimization of loop patterns, INSA Rennes, p.31, 1928. ,
A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems, Conference on Design and Architectures for Signal and Image Processing (DASIP) 2009, pp.8-40, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00429397
Multiprocessor SoC design methods and tools, IEEE Signal Processing Magazine, vol.26, issue.6, pp.72-79, 2009. ,
DOI : 10.1109/MSP.2009.934122
A comparison of synchronous and cycle-static dataflow, Signals, Systems and Computers Conference Record of the Twenty-Ninth Asilomar Conference on, pp.204-210, 1995. ,
Slaheddine Aridhi, and Jean-François Nezan. An open framework for rapid prototyping of signal processing applications, EURASIP journal on embedded systems, issue.11, p.50, 2009. ,
Gartner's 2014 Hype Cycle for Emerging Technologies Maps the Journey to Digital Business, 2014. ,
The hybrid flow shop scheduling problem, European Journal of Operational Research, vol.205, issue.1, pp.1-18, 2010. ,
DOI : 10.1016/j.ejor.2009.09.024
CAPH: A Language for Implementing Stream-Processing Applications on FPGAs, Embedded Systems Design with FPGAs, pp.201-224, 2013. ,
DOI : 10.1007/978-1-4614-1362-2_9
OpenCL: A parallel programming standard for heterogeneous computing systems, Computing in science & engineering, vol.12, issue.3, pp.66-83, 2010. ,
Scenario-aware dataflow: Modeling, analysis and implementation of dynamic applications, 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp.404-411, 2011. ,
DOI : 10.1109/SAMOS.2011.6045491
Overview of the high efficiency video coding (hevc) standard. Circuits and Systems for Video Technology [SPR14] SPRS691e -Multicore Fixed and Floating-Point Digital Signal Processor, IEEE Transactions on, vol.22, issue.122, pp.1649-1668, 2012. ,
Mapping on multi/manycore systems: survey of current and emerging trends A survey of cache coherence schemes for multiprocessors, Proceedings of the 50th Annual Design Automation Conference, pp.13112-13136, 1990. ,
Compositionality in synchronous data flow: Modular code generation from hierarchical sdf graphs, ACM Transactions on Embedded Computing Systems (TECS), vol.12, issue.30, pp.83-114, 2013. ,
A scenario-aware data flow model for combined long-run average and worst-case performance analysis, Proceedings of the Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design MEMOCODE'06. Proceedings .TKA02] William Thies, Michal Karczmarek, and Saman Amarasinghe. StreamIt: A language for streaming applications. In Compiler Construction, pp.185-194, 2002. ,
On computable numbers, with an application to the entscheidungsproblem A programming aid for message-passing systems, Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing, pp.345-363, 1936. ,
Design ip faster: Introducing the chigh-level language, p.23, 2013. ,
Orcc, Proceedings of the 21st ACM international conference on Multimedia, MM '13, pp.863-866, 2013. ,
DOI : 10.1145/2502081.2502231
URL : https://hal.archives-ouvertes.fr/hal-01059858
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio, Journal of Signal Processing Systems, vol.70, issue.2, pp.177-191, 2013. ,
Partial Expansion Graphs: Exposing Parallelism and Dynamic Scheduling Opportunities for DSP Applications, 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, pp.86-93, 2012. ,
DOI : 10.1109/ASAP.2012.14
Design of industrial automated systems via relay ladder logic programming and petri nets. Systems, Man, and Cybernetics , Part C: Applications and Reviews, IEEE Transactions on, vol.28, issue.1 21, pp.137-150, 1998. ,