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F. Caignet, J. H. Collet, F. Sellaye, F. Sellaye, F. Caignet et al., Evolution of intrachip interconnects and performance constraints Bruges (Belgique), 30 Octobre -1er NovembreComparison of Optical and Electrical Interconnects for Intrachip Communications, Conference on VCSELs and Optical Interconnects Signal Propagation on Interconnects Proceedings, pp.51-63, 2002.

E. Sicard, S. Delmas, F. Caignet, C. Cregut, J. G. Caignet et al., Establishement of Signal Integrity Design Rules for CMOS IcsOn-chip Crosstalk Characterization on Deep submicron BusesA Microelectronic Test structure for Signal Integrity Characterization in Deep submicron TechnologyA new methodology for characterization of signal propagation within MicrosystemsA cooperative research for Exp, 4th European symposium on Electromagnetic compatibility Second IEEE International Caracas Conference on Devices, Circuits and Systems (ICCDCS) IEEE International Conference (ICMTS) Design of Circuits and Integrated Systems conference (DCIS) Proceedings of the IEEE 1999 Int. Symposium on EMC 24. S. Delmas -Ben-Dhia, F. Caignet, E. Sicard "A test-vehicle for characterization of sub-micron transistors and interconnects" Proceedings of the ICCDCS conference, pp.67-73, 1998.

E. Sicard, M. Roca, F. Caignet, S. Delmas-ben-dhia, and J. Y. Fourniols, Computer aided prediction of crosstalk effects in CMOS integrated circuits, EMC conference, pp.115-125, 1997.

E. Sicard, M. Roca, F. Caignet, S. Delmas-ben-dhia, J. Y. Fourniols et al., Prediction and Measurement of Crosstalk Effects in Sub-micron CMOS Integrated CircuitsEffects of the Technology Scale Down on the Crosstalk Noise, RADECS'97 Conference PIERS (Progress In Electromagnetics Research Symposium) Mixed Analog and Digital Interface Chip for Low-Cost PC instrumentation, pp.96-116, 1996.

R. Beges, F. Caignet, and N. Nolhier, Transient system-level ESD modeling of an automotive voltage regulator, International ESD Workshop (IEW) Villard de Lans (France), 2014.

B. Courivaud, N. Nolhier, G. Ferru, M. Bafleur, and F. Caignet, Novel 3D back-to-back diodes ESD protection, International ESD Workshop (IEW) Villard de Lans (France), 2014.

D. Trémouilles, N. Monnereau, F. Caignet, and M. Bafleur, Simple ICs-internal-protection models for system level ESD simulation, pp.10-13, 2010.

N. Monnereau, F. Caignet, and D. Trémouilles, Impact of a decoupling capacitance on ESD propagation at system Level : Simulation and Measurement Comparison, pp.10-13, 2010.

F. Caignet, N. Monnereau, and N. Nolhier, Non-invasive system level ESD current measurement using magnetic field probe, pp.10-13, 2010.

N. Lacrampe, F. Caignet, N. Nolhier, and M. Bafleur, VF-TLP based methodology for the prediction of ESD immunity of a PCB, 1st Annual International Electrostatic Discharge Workshop, pp.14-17, 2007.

F. Caignet, J. H. Collet, and F. Sellaye, Evolution of intrachip interconnects and performance constraints, VCSELs and Optical Interconnects, pp.30-31, 2002.
DOI : 10.1117/12.476228

J. H. Collet, F. Selaye, F. Caignet, and D. Litaize, Challenge and Bottlenecks in Computers : the Role of Optics, 2001.

F. Caignet, S. Delmas-ben-dhia, P. Solignac, E. Sicard-travemunde, A. 1. Caignet et al., Measurements of Signal Commutation on Deep sub-micron transistors and interconnectsOn-Chip Signal Integrity Measurement for Complete Deep Sub-micron Interconnect CharacterizationMesure de l'émission parasite d'un oscillateur haute fréquence en 0.18µmSampling Techniques Applied to the Characterization of Signal Propagation in Sub-Micron technology, Propagation on Interconnects 1st IEEE Workshop on Signal Propagation On Interconnects. 13. F. Caignet, E. Sicard, "On the Prediction of Coupling Amplitude in deep submicron VLSI Circuits 1st IEEE Workshop on Signal Propagation on Interconnect, 1997.

F. Caignet and G. Tribet, Mise en évidence de l'influence électromagnétique d'un microprocesseur sur une carte PCB, 2004.

C. Baron, P. B. Aguerre, F. Caignet, A. Ferreira, and J. C. Geffroy, Circuit Fault Detection Using Industrial Cadence Software, pp.221-224, 1998.
DOI : 10.1007/978-94-011-5110-8_55

F. Caignet and E. Sicard, Modélisation prédictive des phénomènes parasites dans les interconnexions des systèmes intégrés, Colloque CAO, 1997.

F. Caignet and A. Ferreira, Utilisation des Outils CAO dans le cadre de la Réalisation et du Test d'un ASIC Mixte Digital/Analogique, Quatrièmes journées pédagogiques, Outil de Simulation et Outil de Conception, 1996.

E. Sicard and F. Caignet, An Educational Project for Microelectronics, Proceedings of the European Workshop, Microelectronics Education, 1996.

. Activité-de-recherche-postérieure and . Au-doctorat, Groupe Photonique du LAAS-CNRS ? Analyse de l'intégration optique dans les puces silicium. En collaboration avec Jacques Collet, Mon travail fût de déterminer l'intérêt de développer des interconnexions optiques dans les puces électroniques. Les analyses ont porté sur une démarche architecturale des micro-processeurs et sur les évolutions technologiques pour les 10 années à venir, Nous avons démontré que malgré les évolutions technologiques, les interconnexions optiques ne seraient pas rentables, 2001.

?. Participation-À-ouvrage, Applications de l'optoélectronique Auteur(s) : Valette, Serge Lavoisier : Chapitre " Quel avenir pour les interconnexions intra-et interpuce ?, pp.223-253, 2002.

?. Intégré-le-groupe and I. , Intégration des Systèmes pour la Gestion de l'Energie ) pour travailler dans l'équipe ESD ? ElectroStatic Discharge (En collaboration avec Marise Bafleur et Nicolas Nolhier, Mes connaissances antérieures en Compatibilité Electromagnétique (CEM) et en intégrité du signal m'ont permis de monter une thématique nouvelle au LAAS : " l'impact des ESD au niveau Système " . Cet axe nécessite un fort développement de nouvelles méthodes de caractérisation et de modélisation

?. Publications-marquantes-du-domaine-monnereau, N. Caignet, F. Tremouilles, and D. , A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis, IEEE Trans. on EMC, issue.1, pp.55-100, 2013.

F. Caignet, N. Nolhier, and M. Bafleur, On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress Issue : 9-11 Special Issue, MICROELECTRONICS RELIABILITY, pp.53-1278

N. Monnereau, F. Caignet, and N. Nolhier, Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models, IEEE Transactions on Device and Materials Reliability, vol.12, issue.4, pp.12-599, 2012.
DOI : 10.1109/TDMR.2012.2218605
URL : https://hal.archives-ouvertes.fr/hal-00941823

?. Monnereau, Développement d'une méthodologie de caractérisation et de modélisation de l'impact des décharges électrostatiques sur les systèmes électroniques, 2011.

?. Sandra and G. Torres, Etude de la robustesse d'amplificateurs embarqués dans des applications portables soumis à des décharges électrostatiques (ESD) au niveau système, Financement CIFRE (On-Semiconductor), encadrement à 80%

?. Animateur-du and D. Ese, Energie pour le Systèmes Embarqués) au Pole Aérospace Valey depuis Avril 2014 Mon expertise dans les domaines de la fiabilité : CEM et EFT, ainsi que mon travail au sein de l'équipe ESE du LAAS ont suscité l'intérêt du pole Aerospace-Valey pour animer ce DAS

?. Organisateur and . Workshop, A2 : IBIS for system level ESD " -pendant la conférence EOS/ESD 2014 ? Tucson Animateurs invités : P. Besse (FREES- CALE), J. Dennihoo (PRAGMA Design), R. Myoung (Ansys) ? Animateur du workshop " A3 : System-Level ESD Protection ? On-Chip or On-Board ?

?. Animateur-de-la-formation, Trouvez des solutions pour réussir dans toutes les phases de vos projets en CEM, Foudre et ESD " organisé par la société NEXIO au LAAS-CNRS, 2014.

?. Domaine-d-'expertise-et-enseignements-montés, E. , M. Smi, M. Dim, M. Eset et al., ESD : intervention dans de nombreuses formations universitaires, niveau M1 et M2, dans un grand nombre de filières Mise en place de TP de simulation CEM sous SPICE. Développement d'une carte de manipulation CEMMise en évidence de l'influence électromagnétique d'un microprocesseur sur une carte PCB, ? CEM, p.1, 2004.

?. Electronique-analogique and ?. , 8hTD : Filtrage ? CAO des circuits numériques ? M1 ESET : 6hC, 4hTD, 16hTP : Introduction à la conception de circuits CMOS (Layout) Mise en place des TP sous SPICE ; mesures des caractéristiques électriques des portes, et conception " Layout " sous " MicroWind

. Td, Développement de TP d'acquisition vidéo et de traitement d'image à base de FPGA. Notion de partitionnement HW/SW, développement de blocs en VHDL, Assemblage d'un système complet pour l'acquisition vidéo