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Générateur de coprocesseur pour le traitement de données en flux (vidéo ou similaire) sur FPGA.

Abstract : Using Field Programmable Gate Arrays (FPGA) is one of the very few solution for real time processingdata flows of several hundreds of Msamples/second. However, using such componentsis technically challenging beyond the need to become familiar with a new kind of dedicateddescription language and ways of describing algorithms, understanding the hardware behaviouris mandatory for implementing efficient processing solutions. In order to circumvent these difficulties,past researches have focused on providing solutions which, starting from a description ofan algorithm in a high-abstraction level language, generetes a description appropriate for FPGAconfiguration. Our contribution, following the strategy of block assembly based on the skeletonmethod, aimed at providing a software environment called CoGen for assembling various implementationsof readily available and validated processing blocks. The resulting processing chainis optimized by including FPGA hardware characteristics, and input and output bandwidths ofeach block in order to provide solution fitting best the requirements and constraints. Each processingblock implementation is either generated automatically or manually, but must complywith some constraints in order to be usable by our tool. In addition, each block developer mustprovide a standardized description of the block including required resources and data processingbandwidth limitations. CoGen then provides to the less experienced user the means to assemblethese blocks ensuring synchronism and consistency of data flow as well as the ability to synthesizethe processing chain in the available hardware resources. This working method has beenapplied to video data flow processing (threshold, contour detection and tuning fork eigenmodesanalysis) and on radiofrequency data flow (wireless interrogation of sensors through a RADARsystem, software processing of a frequency modulated stream, software defined radio).
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Submitted on : Monday, March 21, 2016 - 3:23:12 PM
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  • HAL Id : tel-01291477, version 1


Gwenhael Goavec-Merou. Générateur de coprocesseur pour le traitement de données en flux (vidéo ou similaire) sur FPGA.. Traitement du signal et de l'image [eess.SP]. Université de Franche-Comté, 2014. Français. ⟨NNT : 2014BESA2056⟩. ⟨tel-01291477⟩



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