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Development and characterization of plasma etching processes for the dimensional control and LWR issues during High-k Metal gate stack patterning for 14FDSOI technologies

Abstract : In a transistor manufacturing process, patterning is one of the hardest stages to control. Along with downscaling, the specifications for a transistor manufacturing have tightened up to the nanometer scale. Extreme metrology and process control are required and Critical Dimension Uniformity (CDU) and Line Width Roughness (LWR) have become two of the most important parameters to control.So far, to meet the requirements of the latest CMOS technologies, post-lithography treatments such as plasma cure treatments have been introduced to increase photo-resist stability and to improve LWR prior to pattern transfer. However, conventional post-lithography treatments are no more efficient to address the specifications of14nm gate patterning where more complicated designs are involved.In this work, we have studied limitations of cure pretreatments in 2D gate integrations. In fact, the HBr plasma post-lithography treatment was identified as being responsible of a local pattern shifting that result in a loss of the device’s electrical performance. Preliminary results show that, cure step removal helps to control pattern shifting but to the detriment of the LWR. Indeed, if no cure treatment is introduced in the gate patterning process flow, photoresist patterns undergo severe stress during the subsequent Si-ARC plasma etching in fluorocarbon based plasmas. In this work, the mechanisms that drive such resist degradation in fluorocarbon plasmas have been studied and improved SiARC etch process condition shave been proposed. Besides, we evaluate how the state-of-art gate etch process can be improved, by investigating the impact of each plasma etching step involved in the high-K metal gate patterning on both LWR and gate shifting. The goal of this study is to determine if the TiN metal gate roughness can be modified by changing the gate etch process conditions. Our research reveals that addition of N2 flash steps prevents from gate profile degradation and sidewall roughening. In revenge, the TiN microstructure as well as the HKMG etch process has no impact on the gate final roughness. The hard mask patterning process remains the main contributor for gate roughening.
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Submitted on : Tuesday, March 8, 2016 - 5:21:07 PM
Last modification on : Tuesday, October 19, 2021 - 11:34:38 AM
Long-term archiving on: : Sunday, November 13, 2016 - 11:23:03 AM

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  • HAL Id : tel-01285187, version 1

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Onintza Ros Bengoetxea. Development and characterization of plasma etching processes for the dimensional control and LWR issues during High-k Metal gate stack patterning for 14FDSOI technologies. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2016. English. ⟨NNT : 2016GREAT009⟩. ⟨tel-01285187⟩

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