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C. [. Yang, C. L. Lin, and . Yang, Cache-aware task scheduling on multi-core architecture, International Symposium on VLSI Design Automation and Test (VLSI-DAT), p.139142, 2010.

B. Ghz and .. , execution time on a 16 Threads SMP platform with two Intel Xeon E5620 Processor at 2.4, p.130

T. Black-scholes-programmability-comparison, Line count of the sequential version and the parallel versions using XPU (vectorized), p.131

P. Black-scholes-programmability-comparison, Line count of the sequential version and the vectorized parallel versions using XPU (Vectorized, OpenMP+SSE, p.131

X. , T. , C. Plus, and O. , generates unnecessary idles times when executing certain Task Graphs (DAG) 155 8.4 The super-scalar execution model used by FATMA, SMPSS or Quark executes asynchronously the tasks and use event-based peer-to-peer synchronization model between dependent task, This allows FATMA to eliminate unnecessary idles times when executing Task Graphs, p.155

F. Comparison-between, Q. , and .. , SMPSs implementations of the tiled Cholesky factorization on and 8 Threads Intel Core i7 Q720 processor, p.176

F. Comparison-between and P. , Static Scheduling) implementations of the tiled dgesv on an SMP platform with 2 x Intel Xeon E5620 at 2.4 GHz (16 Hardware Threads), p.178