N. Bambha, Intermediate representations for design automation of multiprocessor DSP systems, Design Automation for Embedded Systems, pp.307-323, 2002.

J. Banâtre and D. L. Métayer, Programming by multiset transformation, Communications of the ACM, vol.36, issue.1, pp.98-111, 1993.
DOI : 10.1145/151233.151242

M. Bariani, P. Lambruschini, and M. Raggio, VC-1 decoder on STMicroelectronics P2012 architecture, Proceedings of 8th Annual Interantional Workshop 'STreaming Day, 2010.

E. Baroth and C. Hartsough, Visual object-oriented programming. chapter Visual Programming in the Real World, pp.21-42, 1995.

S. Shuvra, E. A. Battacharyya, P. K. Lee, and . Murthy, Software Synthesis from Dataflow Graphs, 1996.

V. Bebelis, P. Fradet, A. Girault, and B. Lavigueur, BPDF: A statically analyzable dataflow model with integer and boolean parameters, 2013 Proceedings of the International Conference on Embedded Software (EMSOFT), pp.1-10, 2013.
DOI : 10.1109/EMSOFT.2013.6658581
URL : https://hal.archives-ouvertes.fr/hal-00923672

V. Bebelis, P. Fradet, and A. Girault, A framework to schedule parametric dataflow applications on many-core platforms, Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, pp.125-134
URL : https://hal.archives-ouvertes.fr/hal-00923670

A. Benveniste, P. Bournai, T. Gautier, M. L. Borgne, P. L. Guernic et al., The SIGNAL declarative synchronous language: controller synthesis and systems/architecture design Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems, Proceedings of the 40th IEEE Conference on Decision and Control Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP), pp.3284-3289, 2000.

B. Bhattacharya and S. S. Bhattacharyya, Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001.
DOI : 10.1109/78.950795

S. Shuvra, E. A. Bhattacharyya, and . Lee, Scheduling synchronous dataflow graphs for efficient looping, Journal of VLSI Signal Processing Systems, vol.6, issue.3, pp.271-288, 1993.

S. Shuvra, E. A. Bhattacharyya, and . Lee, Looped schedules for dataflow descriptions of multirate signal processing algorithms. Formal Methods System Design, pp.183-205, 1994.

S. Shuvra, P. K. Bhattacharyya, E. A. Murthy, . Lee, and R. Ap-gan, Complementary heuristics for translating DSP block diagrams into efficient software implementations. Design Automation for Embedded Systems, pp.33-60, 1997.

G. Bilsen, M. Engels, R. Lauwereins, and J. A. Peperstraete, Cyclo-static data flow, 1995 International Conference on Acoustics, Speech, and Signal Processing, pp.3255-3258, 1995.
DOI : 10.1109/ICASSP.1995.479579

B. Bodin, A. M. Kordon, and B. Dupont-de-dinechin, Kperiodic schedules for evaluating the maximum throughput of a synchronous dataflow graph, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp.152-159, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00880624

C. Boeres, J. V. Filho, and V. E. Rebello, A clusterbased strategy for scheduling task on heterogeneous processors, 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp.214-221, 2004.

N. S. Bowen, C. N. Nikolaou, and A. Ghafoor, On the assignment problem of arbitrary process systems to heterogeneous distributed computer systems, IEEE Transactions on Computers, vol.41, issue.3, pp.257-273, 1992.
DOI : 10.1109/12.127439

G. W. Brams, Réseaux de Petri: Théorie et pratique. Number v.1 in Réseaux de Petri, 1983.

D. Brière, D. Ribot, D. Pilaud, and J. Camus, Methods and specifications tools for Airbus on-board systems, Avionics Conference and Exhibition, 1994.

J. T. Buck, Scheduling dynamic dataflow graphs with bounded memory using the token flow model, IEEE International Conference on Acoustics Speech and Signal Processing, 1993.
DOI : 10.1109/ICASSP.1993.319147

J. T. Buck, Static scheduling and code generation from dynamic dataflow graphs with integer-valued control streams, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers, pp.508-513, 1994.
DOI : 10.1109/ACSSC.1994.471505

T. Joseph, E. A. Buck, and . Lee, Scheduling dynamic dataflow graphs with bounded memory using the token flow model, IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.429-432, 1993.

P. Caspi, D. Pilaud, N. Halbwachs, and J. A. Plaice, LUSTRE: a declarative language for real-time programming, Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages , POPL '87, pp.178-188, 1987.
DOI : 10.1145/41625.41641

P. Caspi, G. Hamon, and M. Pouzet, Lucid synchrone: un langage pour la programmation des systèmes réactifs, Systèmes temps réel. Lavoisier, 2007.

G. Edward and . Coffman, Computer and Job Shop Scheduling Theory, 1976.

T. M. Conte, P. K. Dubey, M. D. Jennings, R. B. Lee, A. Peleg et al., Challenges to combining general-purpose and multimedia processors, Computer, vol.30, issue.12, pp.33-37, 1997.
DOI : 10.1109/2.642799

N. Corporation, . Nvidia-cuda-c-programming, and . Guide, NVIDIA Corporation, 4.1 edition, 2012.

N. Cossement, R. Lauwereins, and F. Catthoor, DF*: An extension of synchronous dataflow with data -dependency and nondeterminism, Forum on Design Languages, 2000.

K. Huu and T. Dam, Scheduling of parametric dataflow applications on many-core systems Master's thesis [31] Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, and Henk Corporaal. Modeling static-order schedules in synchronous dataflow graphs, Proceedings of the Conference on Design, Automation Test in Europe (DATE), pp.775-780, 2012.

M. Damavandpeyma, S. Stuijk, M. Geilen, T. Basten, and H. Corporaal, Parametric throughput analysis of scenario-aware dataflow graphs, 2012 IEEE 30th International Conference on Computer Design (ICCD), pp.219-226, 2012.
DOI : 10.1109/ICCD.2012.6378644

M. Damavandpeyma, S. Stuijk, T. Basten, M. Geilen, and H. Corporaal, Throughput-constrained DVFS for scenario-aware dataflow graphs, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.175-184, 2013.
DOI : 10.1109/RTAS.2013.6531090

A. Dasdan and R. K. Gupta, Faster maximum and minimum mean cycle algorithms for system-performance analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, issue.10, pp.889-899, 1998.
DOI : 10.1109/43.728912

J. B. Dennis, First version of a data flow procedure language, Programming Symposium Proceedings Colloque Sur La Programmation, pp.362-376, 1974.
DOI : 10.1007/3-540-06859-7_145

J. Desel and J. Esparza, Free Choice Petri Nets, 1995.
DOI : 10.1017/CBO9780511526558

K. Desnos, M. Pelcat, J. Nezan, S. S. Bhattacharyya, and S. Aridhi, PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp.41-48, 2013.
DOI : 10.1109/SAMOS.2013.6621104
URL : https://hal.archives-ouvertes.fr/hal-00877492

K. Muhammad, I. Dhodhi, A. Ahmad, I. Yatama, and . Ahmad, An integrated technique for task matching and scheduling onto distributed heterogeneous computing systems, Journal of Parallel Distributed Computing, vol.62, issue.9, pp.1338-1361, 2002.

K. Diefendorff and P. K. Dubey, How multimedia workloads will change processor design, Computer, vol.30, issue.9, pp.43-45, 1997.
DOI : 10.1109/2.612247

H. El-rewini and T. G. Lewis, Scheduling parallel program tasks onto arbitrary target machines, Journal of Parallel and Distributed Computing, vol.9, issue.2, pp.138-1530743, 1990.
DOI : 10.1016/0743-7315(90)90042-N

J. Falk, J. Keinert, C. Haubelt, J. Teich, and S. S. Bhattacharyya, A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications, Proceedings of the 7th ACM international conference on Embedded software, EMSOFT '08, pp.189-198, 2008.
DOI : 10.1145/1450058.1450084

E. Robert, D. P. Filman, and . Friedman, Coordinated Computing: Tools and Techniques for Distributed Software, 1984.

P. Fradet, A. Girault, and P. Poplavkoy, SPDF: A schedulable parametric data-flow MoC, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.769-774, 2012.
DOI : 10.1109/DATE.2012.6176572
URL : https://hal.archives-ouvertes.fr/hal-00744376

R. Michael, D. S. Garey, and . Johnson, Computers and Intractability; A Guide to the Theory of NP-Completeness, 1990.

M. Geilen, Reduction techniques for synchronous dataflow graphs, Proceedings of the 46th Annual Design Automation Conference on ZZZ, DAC '09, pp.911-916, 2009.
DOI : 10.1145/1629911.1630146

M. Geilen, Synchronous dataflow scenarios, ACM Transactions on Embedded Computing Systems, vol.10, issue.2, pp.1-16, 2011.
DOI : 10.1145/1880050.1880052
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.468.3718

M. Geilen and T. Basten, Requirements on the Execution of Kahn Process Networks, Proceedings of the 12th European Symposium on Programming , ESOP, pp.319-334, 2003.
DOI : 10.1007/3-540-36575-3_22

M. Amir-hossein-ghamarian, T. Geilen, B. D. Basten, M. R. Theelen, S. Mousavi et al., Liveness and boundedness of synchronous data flow graphs, FMCAD, pp.68-75, 2006.

M. Amir-hossein-ghamarian, S. Geilen, T. Stuijk, B. D. Basten, M. R. Theelen et al., Throughput analysis of synchronous data flow graphs, ACSD, pp.25-36, 2006.

S. Amir-hossein-ghamarian, T. Stuijk, M. Basten, B. D. Geilen, and . Theelen, Latency minimization for synchronous data flow graphs, Euromicro DSD, pp.189-196, 2007.

M. Amir-hossein-ghamarian, T. Geilen, S. Basten, and . Stuijk, Parametric throughput analysis of synchronous data flow graphs, Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp.116-121, 2008.

S. Valentin-gheorghita, M. Palkovic, J. Hamers, A. Vandecappelle, S. Mamagkakis et al., System-scenario-based design of dynamic embedded systems, ACM Transactions on Design Automation of Electronic Systems, vol.14, issue.1, 2009.

A. Girault, B. Lee, and E. A. Lee, Hierarchical finite state machines with multiple concurrency models, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.6, pp.742-760, 1999.
DOI : 10.1109/43.766725

E. Girczyc, Loop winding -a data flow approach to functional pipelining, International Symposium of Circuits and Systems, 1987.

R. Govindarajan, G. R. Gao, and P. Desai, Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks, The Journal of VLSI Signal Processing, vol.31, issue.3, pp.207-2291015452903532, 2002.
DOI : 10.1023/A:1015452903532

P. Grosse, Y. Durand, and P. Feautrier, Methods for power optimization in SOC-based data flow systems, ACM Transactions on Design Automation of Electronic Systems, vol.14, issue.3, 2009.
DOI : 10.1145/1529255.1529260

N. Guan, Z. Gu, W. Yi, and G. Yu, Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphs, 2009 Asia and South Pacific Design Automation Conference, pp.715-720, 2009.
DOI : 10.1109/ASPDAC.2009.4796564

S. Ha and E. A. Lee, Compile-time scheduling and assignment of data-flow program graphs with data-dependent iteration, IEEE Transactions on Computers, vol.40, issue.11, pp.1225-1238, 1991.
DOI : 10.1109/12.102826

S. Ha, S. Kim, C. Lee, Y. Yi, S. Kwon et al., PeaCE, ACM Transactions on Design Automation of Electronic Systems, vol.12, issue.3, pp.1-24, 2008.
DOI : 10.1145/1255456.1255461
URL : https://hal.archives-ouvertes.fr/hal-01274178

D. S. Hochbaum, Approximation Algorithms for NP-hard Problems, 1997.

A. W. Holt, H. Saint, R. Shapiro, and S. Warshall, Final report on the information systems theory project, 1968.

C. Hsu, M. Ko, and S. S. Bhattacharyya, Software synthesis from the dataflow interchange format, Proceedings of the 2005 workshop on Software and compilers for embedded systems , SCOPES '05, pp.37-49, 2005.
DOI : 10.1145/1140389.1140394

C. Hwang, Y. Hsu, and Y. Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation conference , DAC '91, pp.764-769, 1991.
DOI : 10.1145/127601.127766

M. A. Iverson, F. Özgüner, and G. J. Follen, Parallelizing existing applications in a distributed heterogeneous environment, 4th Heterogeneous Computing Workshop (HCW), pp.93-100, 1995.

W. Gary and . Johnson, LabVIEW Graphical Programming, 2006.

W. M. Johnston, J. R. Hanna, and R. J. Millar, Advances in dataflow programming languages, ACM Computing Surveys, vol.36, issue.1, pp.1-34, 2004.
DOI : 10.1145/1013208.1013209

G. Kahn, The semantics of simple language for parallel programming, IFIP Congress, pp.471-475, 1974.

H. Kalva and J. Lee, The VC-1 Video Coding Standard, IEEE Multimedia, vol.14, issue.4, pp.88-91, 2007.
DOI : 10.1109/MMUL.2007.86

R. M. Karp, A characterization of the minimum cycle mean in a digraph, Discrete Mathematics, vol.23, issue.1, pp.309-311, 1978.
DOI : 10.1016/0012-365X(78)90078-X

H. Kee, C. Shen, S. S. Bhattacharyya, I. C. Wong, Y. Rao et al., Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware, Journal of Signal Processing Systems, vol.55, issue.6, pp.285-301, 2012.
DOI : 10.1007/s11265-011-0599-5

S. Cheol, K. , and S. Lee, Push-pull: guided search DAG scheduling for heterogeneous clusters, International Conference on Parallel Processing (ICPP), pp.603-610, 2005.

D. Ko and S. S. Bhattacharyya, Dynamic configuration of dataflow graph topology for DSP system design, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.69-72, 2005.

M. Ko, C. Zissulescu, S. Puthenpurayil, S. S. Bhattacharyya, B. Kienhuis et al., Parameterized looped schedules for compact representation of execution sequences in dsp hardware and software implementation, IEEE Transactions on Signal Processing, vol.55, issue.6, pp.3126-3138, 2007.

F. Kong, W. Yi, and Q. Deng, Energy-efficient scheduling of real-time tasks on cluster-based multicores, Proceedings of the Conference on Design Automation Test in Europe (DATE), pp.1135-1140, 2011.

E. A. Lee, Recurrences, iteration, and conditionals in statically scheduled block diagrams languages, VLSI Signal Processing III, chapter 31, pp.330-340, 1988.

E. A. Lee, Embedded Software, Advances in Computers, 2002.
DOI : 10.1016/S0065-2458(02)80004-3

A. Edward, S. Lee, and . Ha, Scheduling strategies for multiprocessor real-time DSP, IEEE Global Telecommunications Conference and Exhibition (GLOBECOM), pp.1279-1283, 1989.

A. Edward, D. G. Lee, and . Messerschmitt, Synchronous data flow, Proceedings of the IEEE, pp.1235-1245, 1987.

A. Edward, D. G. Lee, and . Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on Computers, vol.36, issue.1, pp.24-35, 1987.

J. Lee and H. Kalva, The VC-1 and H.264 Video Compression Standards for Broadband Video Services, 2008.
DOI : 10.1007/978-0-387-71043-3

Y. Wan and . Lee, Energy-saving DVFS scheduling of multiple periodic realtime tasks on multi-core processors, Distributed Simulation and Real- Time Applications (DS-RT), pp.216-223, 2009.

G. Legoff, Using synchronous languages for interlocking, International Conference on Computer Application in Transportation Systems, 1996.

E. Charles, J. B. Leiserson, and . Saxe, Retiming synchronous circuitry, Algorithmica, vol.6, issue.1, pp.5-35, 1991.

J. Lu and Y. Guo, Energy-Aware Fixed-Priority Multi-core Scheduling for Real-Time Systems, 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications, pp.277-281, 2011.
DOI : 10.1109/RTCSA.2011.25

S. Ritz, M. Pankert, O. Mauss, and H. Meyr, Dynamic data flow and control flow in high level DSP code synthesis, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pages II.449? II.452, 1994.

O. Marchetti and A. Munier-kordon, A sufficient condition for the liveness of weighted event graphs, European Journal of Operational Research, vol.197, issue.2, pp.532-540, 2009.
DOI : 10.1016/j.ejor.2008.07.037
URL : https://hal.archives-ouvertes.fr/hal-01197183

D. Melpignano, L. Benini, E. Flamand, B. Jego, T. Lepley et al., Platform 2012, a many-core computing accelerator for embedded SoCs, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.1137-1142
DOI : 10.1145/2228360.2228568

K. Praveen, E. A. Murthy, and . Lee, Multidimensional synchronous dataflow, IEEE Transactions on Signal Processing, vol.50800830, issue.8, pp.2064-2079, 2002.

K. Praveen, S. S. Murthy, E. A. Bhattacharyya, and . Lee, Combined code and data minimization for synchronous dataflow programs, Memorandum UCB, vol.93, 1994.

H. Oh and S. Ha, Fractional rate dataflow model and efficient code synthesis for multimedia applications, Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), pp.12-17, 2002.

K. Keshab, D. G. Parhi, and . Messerschmitt, Rate-optimal fully-static multiprocessor scheduling of data-flow signal processing programs, IEEE International Symposium on Circuits and Systems, 1923.

C. Park, J. Chung, and S. Ha, Extended synchronous dataflow for efficient DSP system prototyping, Proceedings of IEEE International Workshop on Rapid System Prototyping (RSP), pp.196-201, 1999.

T. M. Parks, Bounded Scheduling of Process Networks, 1995.

T. M. Parks, L. Pino, and E. A. Lee, A comparison of synchronous and cycle-static dataflow, Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, pp.204-210, 1995.
DOI : 10.1109/ACSSC.1995.540541

J. Peterson, Petri Net Theory and the Modeling of Systems, 1981.

C. Adam and P. , Kommunikation mit Automaten, 1962.

J. Piat, S. S. Bhattacharyya, and M. Raulet, Interfacebased hierarchy for synchronous data-flow graphs, Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS), pp.145-150, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00440478

J. Luis-pino, S. S. Bhattacharyya, and E. A. Lee, A hierarchical multiprocessor scheduling system for DSP applications, Conference Record of the Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, pp.122-126, 1995.

W. Plishker, N. Sane, M. Kiemb, K. Anand, and S. S. Bhattacharyya, Functional DIF for Rapid Prototyping, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, pp.17-23, 2008.
DOI : 10.1109/RSP.2008.32

W. Plishker, N. Sane, and S. S. Bhattacharyya, A generalized scheduling approach for dynamic dataflow applications, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.111-116, 2009.
DOI : 10.1109/DATE.2009.5090642

W. Plishker, N. Sane, M. Kiemb, and S. S. Bhattacharyya, Heterogeneous design in functional DIF, Transactions on HiPEAC, vol.4, pp.391-408, 2011.

C. Ptolemaeus, System Design, Modeling, and Simulation using Ptolemy II

S. Ranaweera and D. P. Agrawal, A task duplication based scheduling algorithm for heterogeneous systems, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000, pp.445-450, 2000.
DOI : 10.1109/IPDPS.2000.846020

R. Reiter, Scheduling Parallel Computations, Journal of the ACM, vol.15, issue.4, pp.590-599, 1968.
DOI : 10.1145/321479.321485

S. Ritz, M. Pankert, and H. Meyr, High level software synthesis for signal processing systems, [1992] Proceedings of the International Conference on Application Specific Array Processors, pp.679-693, 1992.
DOI : 10.1109/ASAP.1992.218536

S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. López-lagunas et al., A bandwidthefficient architecture for media processing, Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp.3-13, 1998.

Y. Robert and F. Vivien, Introduction to Scheduling, 2009.
DOI : 10.1201/9781420072747
URL : https://hal.archives-ouvertes.fr/hal-00786389

E. Seo, J. Jeong, S. Park, and J. Lee, Energy efficient scheduling of real-time tasks on multicore processors, IEEE Transactions on Parallel Distributed Systems, vol.19, issue.11, pp.1540-1552, 2008.

C. Shen, S. Wu, N. Sane, H. Wu, W. Plishker et al., Design and Synthesis for Multimedia Systems Using the Targeted Dataflow Interchange Format, IEEE Transactions on Multimedia, vol.14, issue.3, pp.3-1630, 2012.
DOI : 10.1109/TMM.2012.2191397

C. Gilbert, E. A. Sih, and . Lee, A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures, IEEE Transactions on Parallel Distributed Systems, vol.4, issue.2, pp.175-187, 1993.

S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization, 2000.
DOI : 10.1201/9781420048025

J. E. Stone, D. Gohara, and G. Shi, OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems, Computing in Science & Engineering, vol.12, issue.3, pp.66-73, 2010.
DOI : 10.1109/MCSE.2010.69

S. Stuijk, M. Geilen, and T. Basten, SDF^3: SDF For Free, Sixth International Conference on Application of Concurrency to System Design (ACSD'06), pp.276-278, 2006.
DOI : 10.1109/ACSD.2006.23

S. Stuijk, M. Geilen, and T. Basten, Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs, IEEE Transactions on Computers, vol.57, issue.10, pp.1331-1345, 2008.
DOI : 10.1109/TC.2008.58
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.78.5393

J. Gary, J. Sullivan, W. Ohm, T. Han, and . Wiegand, Overview of the high efficiency video coding (HEVC) standard, IEEE Transactions on Circuits and Systems for Video Technology, pp.1649-1668, 2012.

B. D. Theelen, M. Geilen, T. Basten, J. Voeten, S. V. Gheorghita et al., A scenario-aware data flow model for combined long-run average and worst-case performance analysis, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings., pp.185-194, 2006.
DOI : 10.1109/MEMCOD.2006.1695924

W. Thies, M. Karczmarek, and S. P. Amarasinghe, StreamIt: A Language for Streaming Applications, Proceedings of the 11th International Conference on Compiler Construction, pp.179-196, 2002.
DOI : 10.1007/3-540-45937-5_14

H. Topcuoglu, S. Hariri, and M. Wu, Performance-effective and low-complexity task scheduling for heterogeneous computing, IEEE Transactions on Parallel and Distributed Systems, vol.13, issue.3, pp.260-274, 2002.
DOI : 10.1109/71.993206

M. Viitanen, J. Vanne, T. D. Hamalainen, M. Gabbouj, and J. Lainema, Complexity analysis of next-generation HEVC decoder, 2012 IEEE International Symposium on Circuits and Systems, pp.882-885, 2012.
DOI : 10.1109/ISCAS.2012.6272182

W. William, E. A. Wadge, and . Ashcroft, LUCID, the Dataflow Programming Language, 1985.

P. Wauters, M. Engels, R. Lauwereins, and J. A. Peperstraete, Cyclo-dynamic dataflow, Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing, pp.319-326, 1996.
DOI : 10.1109/EMPDP.1996.500603

M. Wiggers, M. Bekooij, and G. J. Smit, Buffer Capacity Computation for Throughput Constrained Streaming Applications with Data-Dependent Inter-Task Communication, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium, pp.183-194, 2008.
DOI : 10.1109/RTAS.2008.10

M. Wipliez, G. Roquier, and J. Nezan, Software Code Generation for the RVC-CAL Language, Journal of Signal Processing Systems, vol.29, issue.12, pp.203-213, 2011.
DOI : 10.1007/s11265-009-0390-z
URL : https://hal.archives-ouvertes.fr/hal-00407950

S. Wu, C. Shen, N. Sane, K. Davis, and S. S. Bhattacharyya, Parameterized scheduling for signal processing systems using topological patterns, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1561-1564, 2012.
DOI : 10.1109/ICASSP.2012.6288190

X. Wu, Y. Lin, J. Han, and J. Gaudiot, Energyefficient scheduling of real-time periodic tasks in multicore systems, Network and Parallel Computing (NPC), pp.344-357, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01054974