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Conception d'amplificateurs de puissance hautement linéaires à 60 GHz en technologies CMOS nanométriques

Abstract : The CMOS 60GHz power amplifier (PA) remains one of the most design-challenging components. Indeed, a high linearity associated with a large back-off range are required due to complex modulated signals.In this context, this work focuses on the design of architectures and linearization techniques which are usable at millimeter-wave frequencies. First, a CMOS PA state of the art is presented to define all bottlenecks. Then, the physical phenomena impacting on passive device performances are described. Elementary PAs are implemented in CMOS 65nm and 28nm Bulk and the most suitable topologies are selected. Finally, two highly linear circuits are designed in 65nm Bulk and 28nm FD-SOI. They achieve the highest ITRS figures of merit reported to this day. In addition, the 28nm FD-SOI PA exhibits the best linearity/consumption tradeoff.
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  • HAL Id : tel-01142532, version 1

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Aurélien Larie. Conception d'amplificateurs de puissance hautement linéaires à 60 GHz en technologies CMOS nanométriques. Electronique. Université de Bordeaux, 2014. Français. ⟨NNT : 2014BORD0210⟩. ⟨tel-01142532⟩

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