I. Belaid, F. Muller, M. Benjemaa, and A. Giulieri, Off-line placement of hardware tasks on FPGA, 2009 International Conference on Field Programmable Logic and Applications, pp.10-11, 2009.
DOI : 10.1109/FPL.2009.5272402
URL : https://hal.archives-ouvertes.fr/hal-00524957

C. Foucher, F. Muller, and A. Giulieri, Implémentation d'un système d'exploitation matériel compatible rtems, Colloque GDR SoC/SiP, pp.10-11, 2009.

B. Ouni, F. Muller, and M. Benjemaa, Placement et ordonnancement des tâches matérielles sur des zones reconfigurables en utilisant le bees algorithm, Colloque GDR SoC/SiP, pp.10-11, 2009.

F. Muhammad, K. Bhatti-muhammad, F. Muller, and M. Auguin, Efficient and optimal multiprocessor scheduling for real time tasks, Colloque GDR SoC/SiP, pp.4-5, 2008.

I. Belaid, F. Muller, and A. Giulieri, Virtualisation de l'ordonnancement matériel/logiciel sur plateforme reconfigurable dynamiquement, Colloque GDR SoC/SiP, pp.4-5, 2008.

F. Muhammad, F. Muller, and M. Auguin, Proportionate scheduling of hard and soft real time tasks, Colloque GDR SoC/SiP, pp.13-14, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00525319

F. Muller and J. Calvez, Mcse toolbox : Prototype d'outil pour la conception des systèmes matériels/logiciels, Colloque CAO de circuits intégrés et systèmes, pp.10-12, 1999.

F. Muller, J. Calvez, and R. Gasmann, Génération d'interfaces matériel/logiciel , expérimentation pour un bus à microprocesseur, Séminaire CoDesign, pp.25-1996

F. Muller, Rtos pour ar, Journée Thématique Architecture Reconfigurable, pp.11-12, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00525018

I. Belaid and F. Muller, Dynamic partial reconfiguration in sopc, Journée Industriel, p.29, 2008.

J. Et-colloques-À-caractère-pédagogique, F. Muller, and G. Jacquemod, Validation de soc : Les étudiants se forment à l'émulation sous veloce, Journal La Puce à l'Oreille, p.4, 2009.

F. Muller, G. Jacquemod, and R. Bouchakour, Vérification de soc sous veloce, Journées Pédagogiques CNFM, pp.26-28, 2008.

B. Muller-fabrice, E. Fontaine, R. Meneceur, and . Meyer, Développement d'un simulateur automobile pour la validation d'un rtos matériel, Les Neuvièmes Journées pédagogiques du CNFM, pp.22-24, 2006.

F. Muller, É. Dekneuvel, and M. Auguin, Intégration de modules ip sur une carte de prototypage excalibur-nios, Les Septièmes Journées pédagogiques du CNFM, pp.27-29, 2002.

C. L. Liu and J. W. Layland, Scheduling algorithms for multiprogramming in a hardreal-time environment, Journal of the ACM, 1973.

Z. Pan and B. E. Wells, Hardware supported tasks scheduling on dynamically reconfigurable soc architectures, IEEE transactions on very large scale integration (VLSI) systems, pp.1465-1473, 2008.

D. T. Pham, A. Ghanbarzadeh, E. Koç, S. Otri, M. Rahim-sand et al., The Bees Algorithm ??? A Novel Tool for Complex Optimisation Problems, Innovative Production Machines and Systems, 2006.
DOI : 10.1016/B978-008045157-2/50081-X

F. Redaelli, M. D. Santambrogio, and M. , An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures, 2008 International Conference on Reconfigurable Computing and FPGAs, pp.97-102, 2008.
DOI : 10.1109/ReConFig.2008.42

F. E. Sandnes and G. M. Megson, Improved Static Multiprocessor Scheduling using Cyclic Task Graphs: A Genetic Approach, Parallel Computing : Fundamentals, Applications and New Directions, vol.12, pp.703-710, 1998.
DOI : 10.1016/S0927-5452(98)80092-0

F. E. Sandnes and O. Sinnen, A new strategy for multiprocessor scheduling of cyclic task graphs, International Journal of High Performance Computing and Networking, vol.3, issue.1, pp.62-71, 2005.
DOI : 10.1504/IJHPCN.2005.007868

Y. Yi, W. Han, X. Zhao, A. T. Erdogan, and T. Arslan, An ilp formulation for task mapping and scheduling on multicore architectures, Design, Automation and Test in Europe (DATE), pp.33-38, 2009.

R. Dobrin and G. Fohler, Reducing the number of preemptions in standard fixed priority scheduling, 2004.

S. Oh and S. Yang, A modified least-laxity-first scheduling algorithm for realtime tasks, Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications, RTCSA '98, p.31, 1998.

W. Kim and J. Kim, Preemption-aware dynamic voltage scaling in hard real-time systems, Proceedings of the 2004 international symposium on Low power electronics and design , ISLPED '04, pp.393-398, 2004.
DOI : 10.1145/1013235.1013328

S. Baruah, The limited-preemption uniprocessor scheduling of sporadic task systems, Proceedings of the 17th Euromicro Conference on Real-Time Systems, pp.137-144, 2005.

M. Moir and S. Ramamurthy, Pfair scheduling of fixed and migrating periodic tasks on multiple resources, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054), p.294, 1999.
DOI : 10.1109/REAL.1999.818857

L. George, N. Rivierre, and M. Spuri, Ordonnancement de Tâches efficace et à Complexité Maîtrisée pour des Systèmes Temps Réel, 2009.

M. Litzkow, M. Livny, and M. Mutka, Condor-a hunter of idle workstations, [1988] Proceedings. The 8th International Conference on Distributed, 1988.
DOI : 10.1109/DCS.1988.12507

H. Casanova and J. Dongarra, NetSolve, Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) , Supercomputing '96, 1995.
DOI : 10.1145/369028.369111

D. Abramson, R. Sosic, J. Giddy, and B. Hall, Nimrod: a tool for performing parametrised simulations using distributed workstations, Proceedings of the Fourth IEEE International Symposium on High Performance Distributed Computing, 1995.
DOI : 10.1109/HPDC.1995.518701

D. Thain and M. Livny, Building reliable clients and servers The Grid : Blueprint for a New Computing Infrastructure, 2003.

G. Sabin, R. Kettimuthu, and A. Rajan, Scheduling of Parallel Jobs in a Heterogeneous Multi-site Environment, the Proc. of the 9th International Workshop on Job Scheduling Strategies for Parallel Processing, pp.87-104, 2003.
DOI : 10.1007/10968987_5

K. Paulsson, M. Hübner, J. Becker, J. Philippe, and C. Gamrat, On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ??THER Project, 2007 International Conference on Field Programmable Logic and Applications, pp.415-422, 2007.
DOI : 10.1109/FPL.2007.4380682

K. Compton and S. Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys, vol.34, issue.2, pp.171-210, 2002.
DOI : 10.1145/508352.508353

C. Kao, Benefits of Partial Reconfiguration, Xcell Journal, vol.55, pp.65-67, 2005.

P. Manet, D. Maufroid, L. Tosi, G. Gailliard, O. Mulertt et al., An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications, EURASIP Journal on Embedded Systems, vol.2005, issue.55, pp.1-1, 2008.
DOI : 10.1109/JSSC.2007.909344

S. Imran-rafiq-quadri, J. Meftali, and . Dekeyser, MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs, Sixth IEEE Workshop on

E. El-araby, I. Gonzalez, and T. El-ghazawi, Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing, ACM Transactions on Reconfigurable Technology and Systems, vol.1, issue.4, pp.1-2123, 2009.
DOI : 10.1145/1462586.1462590

J. Antonio-casas, J. M. Moreno, J. Madrenas, and J. Cabestany, A novel hardware architecture for self-adaptive systems, AHS '07 : Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems, pp.592-599, 2007.

I. Xilinx, Virtex-5 FPGA Configuration User Guide, 2010.

K. Compton and S. Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys, vol.34, issue.2, pp.171-210, 2002.
DOI : 10.1145/508352.508353

R. Tessier and W. Burleson, Reconfigurable computing for digital signal processing : A survey, The Journal of VLSI Signal Processing, vol.28, issue.1/2, pp.7-27, 2001.
DOI : 10.1023/A:1008155020711

K. Paulsson, M. Hübner, S. Bayar, and J. Becker, Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems, Field Programmable Logic and Applications FPL 2008. International Conference on, pp.699-700, 2008.

S. Guccione, D. Levi, and P. Sundararajan, JBits : Java based interface for reconfigurable computing, 1999.

M. Liu, W. Kuehn, Z. Lu, and A. Jantsch, Run-time Partial Reconfiguration speed investigation and architectural design space exploration, 2009 International Conference on Field Programmable Logic and Applications, 2009.
DOI : 10.1109/FPL.2009.5272463

F. Redaelli, M. D. Santambrogio, and D. Sciuto, Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems, Proceedings of the conference on Design, automation and test in Europe, DATE '08, pp.519-522, 2008.

A. Flynn, A. Gordon-ross, and A. D. George, Bitstream relocation with local clock domains for partially reconfigurable FPGAs, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.300-303, 2009.
DOI : 10.1109/DATE.2009.5090676

. Xilinx, Real-Time Executive for Multiprocessor Systems (RTEMS) web site, 2011.

. Gaisler, Disponible également sur le site : RCC (RTEMS LEON/ERC32 GNU crosscompiler system) permettant la compilation RTEMS pour LEON3, 2011.

P. , D. Stotts, and W. Pugh, Parallel finite automata for modeling concurrent software systems, J. Syst. Softw, vol.27, pp.27-43, 1994.

D. Bailey, E. Barszcz, J. Barton, D. Browning, R. Carter et al., The NAS Parallel Benchmarks, 1994.

J. P. Calvez and D. Isidoro, A CoDesign experience with the MCSE methodology, Third International Workshop on Hardware/Software Codesign, pp.140-147, 1994.
DOI : 10.1109/HSC.1994.336713

D. Heller, P. Bakowski, and J. P. Calvez, Functional-level synthesis with vhdl, EU- ROVHDL'93, 1993.

J. P. Calvez, Asics specification and design, Chapman&Hall, pp.1-570, 1995.

A. Bunker and G. Gopalakrishnan, Formal specification of the virtual component interface standard in the unified modeling language, 2001.

P. Kwan and C. Clarke, FPGAs for Improved Energy Efficiency in Processor Based Systems, Thambipillai Srikanthan, Jingling Xue Advances in Computer Systems Architecture, pp.440-449, 1007.
DOI : 10.1007/11572961_35

J. Eker and J. W. Janneck, Cal language report, language version 1.0 -document edition 1, 2003.

C. W. Fletcher, I. A. Lebedev, N. B. Asadi, D. R. Burke, and J. Wawrzynek, Bridging the GPGPU-FPGA efficiency gap, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '11, pp.119-122, 2011.
DOI : 10.1145/1950413.1950439

A. Papakonstantinou, K. Gururaj, J. A. Stratton, D. Chen, J. Cong et al., FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs, 2009 IEEE 7th Symposium on Application Specific Processors, pp.35-42, 2009.
DOI : 10.1109/SASP.2009.5226333

S. Deshanand, Higher level programming abstractions for fpgas using opencl The Role of FPGAs in a Converged Future with Heterogeneous Programmable Processors, Session Future-Looking CAD/Compiler Synthesis Flows, FPGA 2011 Pre-Conference Workshop, 2011.

D. Chen, C. Deming, T. Sansiri, and W. Wei, Performance and power evaluation of a 3d cmos/nanomaterial reconfigurable architecture, International Conference on Computer Aided Design, pp.758-764, 2007.

M. Caccamo, G. Buttazzo, and L. Sha, Capacity sharing for overrun control, Proceedings 21st IEEE Real-Time Systems Symposium, pp.295-304, 2000.
DOI : 10.1109/REAL.2000.896018

D. Stewart and P. K. Khosla, Real-time scheduling of sensor-based control systems, Real-Time Programming (W. Halang), pp.144-150, 1991.

F. Behmann, Nextgen multicore/accelerators soc platform defined by itrs, 2010.

K. Jeffay and S. Goddard, Rate-Based Resource Allocation Models for Embedded Systems, Proc. First International Workshop on Embedded Software, 2001.
DOI : 10.1007/3-540-45449-7_14

L. Abeni, G. Lipari, G. Buttazzo, S. Superiore, and S. Anna, Constant bandwidth vs. proportional share resource allocation, Proceedings IEEE International Conference on Multimedia Computing and Systems, pp.107-111, 1999.
DOI : 10.1109/MMCS.1999.778154

I. Stoica, H. Abdel-wahab, K. Jeffay, S. K. Baruah, J. E. Gehrke et al., A proportional share resource allocation algorithm for real-time, time-shared systems, 17th IEEE Real-Time Systems Symposium, 1996.
DOI : 10.1109/REAL.1996.563725

K. A. Williams and . Yelick, The landscape of parallel computing research : a view from Berkeley, 2006.

R. Kumar, T. Patra, and A. Basu, Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs, High Performance Computing, pp.435-4383, 2006.
DOI : 10.1007/3-540-47847-7_28

F. Muhammad, M. Auguin, and F. Muller, Procédé de gestion des préemptions dans un système d'exploitation temps réel, n ? d'application wo, 2008.

F. Duhem, F. Muller, and P. Lorenzini, Reconfiguration time overhead on fpga : Reduction and cost model (accepted). IET Computers and Digital Techniques, 2011.

I. Belaid, F. Muller, and M. Benjemaa, Static scheduling of periodic hardware tasks with precedence and deadline constraints on reconfigurable hardware devices . Special Issue in EURASIP, International Journal of Reconfigurable Computing, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00661583

I. Belaid, F. Muller, and M. Benjemaa, New three-level resource management enhancing quality of off-line hardware task placement on fpga, EURASIP International Journal of Reconfigurable Computing, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00519278

I. Belaid, F. Muller, and M. Benjemaa, Algorithm-Architecture Matching for Signal and Image Processing : "A New Three-Level Strategy for Off-line Placement

F. Muhammad, K. Bhatti, F. Muller, and M. Auguin, Precognitive dvfs : Minimizing switching points to further reduce the energy consumption, 14th IEEE Real-Time and Embedded Technology and Applications Symposium, WIP session, pp.22-24, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00367647

F. Muhammad, F. Muller, and M. Auguin, Weight Bound Limits in Supertasking Approach for Guaranteed Timeline Constraints, 2008 International Conference on Parallel Processing, Workshops, pp.9-16, 2008.
DOI : 10.1109/ICPP-W.2008.24

F. Muhammad, F. Muller, and M. Auguin, Hierarchical scheduling approach for real time tasks, Proc. International Conference on Parallel Processing, Workshop on Scheduling Ressource Management for Parallel and Distributed Systems, pp.8-12, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00367654

F. Muhammad, F. Muller, and M. Auguin, Aether : dynamic and selfadaptive middleware, Proc. IEEE International Multitopic Conference, pp.28-30, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00525310

F. Muhammad, F. Muller, and M. Auguin, Dynamic and Self adaptive Resource Management: ??THER Operating Environment, 2007 International Conference on Emerging Technologies, pp.12-13, 2007.
DOI : 10.1109/ICET.2007.4516329

F. Muhammad, F. Muller, and M. Auguin, Self balancing computational load on multiprocessor architecture, IEEE International Conference on Self-Organization and Autonomous Systems in Computing and Communications - SOAS'2006, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00525091

F. Muhammad, F. Muller, and M. Auguin, Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks, Proceedings of the 2006 ACM symposium on Applied computing , SAC '06, 2006.
DOI : 10.1145/1141277.1141623
URL : https://hal.archives-ouvertes.fr/hal-00525035

F. Duhem, F. Muller, and P. Lorenzini, Transaction-level modeling of dynamically reconfigurable systems using systemc, Sophia Antipolis MicroElectronics , SAME'2011, Poster session), 2011.

F. Muller and F. Muhammad, Virtual platform for hw rtos -multiprocessor hardware rtos, IEEE in Proc. Design Automation and Test in Europe, pp.21-23, 2009.

J. Diguet, M. Khodary, G. Gogniat, F. Muller, and M. Auguin, On simulating operating environment decisions in a sane network, AMWAS'08 (2nd AETHER - MORPHEUS Workshop-Autumn School From Reconfigurable to Self-Adaptive Computing), 2008.

F. Muller, F. Muhammad, and M. Auguin, Design of a hardware multiprocessor real-time operating system, IEEE in Proc. Design Automation and Test in Europe, pp.17-19, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00525314

C. Foucher, F. Muller, and A. Giulieri, M??thodologie d??di??e aux applications parall??les sur plateforme reconfigurable dynamiquement, Techniques et sciences informatiques, vol.32, issue.2, 2011.
DOI : 10.3166/tsi.32.253-280

F. Duhem, F. Muller, and P. Lorenzini, Dynamic and partial reconfiguration transaction-level modeling in systemc, Colloque GDR SoC/SiP, pp.15-17, 2011.

C. Foucher, F. Muller, and A. Giulieri, Flot de conception d'applications parallèles sur plateforme reconfigurable dynamiquement, Symposium en Architectures nouvelles de machines (Sympa'14), pp.10-13, 2011.

I. Belaid, F. Muller, and M. Benjemaa, Off-line placement/scheduling of hardware tasks on reconfigurable devices, Colloque GDR SoC/SiP, pp.9-11, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00521199

F. Duhem, F. Muller, and P. Lorenzini, Services pour des systèmes reconfigurables dynamiquement, Colloque GDR SoC/SiP, pp.9-11, 2010.

C. Foucher, F. Muller, and A. Giulieri, Implémentation d'un système d'exploitation matériel compatible rtems, Colloque GDR SoC/SiP, pp.10-11, 2009.

B. Ouni, F. Muller, and M. Benjemaa, Placement et ordonnancement des tâches matérielles sur des zones reconfigurables en utilisant le bees algorithm, Colloque GDR SoC/SiP, pp.10-11, 2009.

F. Muhammad, K. Bhatti-muhammad, F. Muller, and M. Auguin, Efficient and optimal multiprocessor scheduling for real time tasks, Colloque GDR SoC/SiP, pp.4-5, 2008.

I. Belaid, F. Muller, and A. Giulieri, Virtualisation de l'ordonnancement matériel/logiciel sur plateforme reconfigurable dynamiquement, Colloque GDR SoC/SiP, pp.4-5, 2008.

F. Muhammad, F. Muller, and M. Auguin, Proportionate scheduling of hard and soft real time tasks, Colloque GDR SoC/SiP, pp.13-14, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00525319

F. Muller, &. Os, G. Colloque, /. Soc, . Sip et al., Improving utilization of reconfigurable resources using two dimensional compaction, juin 2008. References [1] Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '07), pp.4-5, 2007.

I. Belaid, F. Muller, and M. Benjemaa, Off-line placement of hardware tasks on FPGA, 2009 International Conference on Field Programmable Logic and Applications, pp.591-595, 2009.
DOI : 10.1109/FPL.2009.5272402
URL : https://hal.archives-ouvertes.fr/hal-00524957

K. Bazargan, R. Kastner, and M. Sarrafzadeh, Fast template placement for reconfigurable computing systems, IEEE Design & Test of Computers, vol.17, issue.1, pp.68-83, 2000.
DOI : 10.1109/54.825678

E. G. Coffman-jr, M. R. Garey, and D. S. Johnson, Approximation Algorithms for Bin-Packing ??? An Updated Survey, 1997.
DOI : 10.1007/978-3-7091-4338-4_3

H. Walder, C. Steiger, and M. Platzner, Fast online task placement on FPGAs: free space partitioning and 2D-hashing, Proceedings International Parallel and Distributed Processing Symposium, p.178, 2003.
DOI : 10.1109/IPDPS.2003.1213329

A. Ahmadinia, C. Bobda, M. Bednara, and J. Teich, A new approach for on-line placement on reconfigurable devices, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., p.134, 2004.
DOI : 10.1109/IPDPS.2004.1303104

T. Marconi, Y. Lu, K. Bertels, and G. Gaydadjiev, Intelligent merging online task placement algorithm for partial reconfigurable systems, Proceedings of the conference on Design, automation and test in Europe, DATE '08, pp.1346-1351, 2008.
DOI : 10.1145/1403375.1403699

M. Handa and R. Vemuri, An efficient algorithm for finding empty space for online FPGA placement, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.960-965, 2004.
DOI : 10.1145/996566.996820

H. Elgindy, M. Middendorf, H. Schmeck, and B. Schmidt, Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer, Proceedings of the Field Programmable Logic and Applications, pp.379-388, 2000.
DOI : 10.1007/3-540-44614-1_41

J. Resano, D. Mozos, D. Verkest, S. Vernalde, and F. Catthoor, Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems, Proceedings of the International Conference on Field Programmable Logic and Application, pp.585-594, 2003.
DOI : 10.1007/978-3-540-45234-8_57

E. M. Panainte, K. Bertels, and S. Vassiliadis, FPGA-area allocation for partial run-time reconfiguration, Proceedings of the Design Automation Test Europe (DATE '05), pp.100-105, 2005.

A. Lodi, S. Martello, and M. Monaci, Two-dimensional packing problems: A survey, European Journal of Operational Research, vol.141, issue.2, pp.241-252, 2002.
DOI : 10.1016/S0377-2217(02)00123-6

A. Lodi, S. Martello, and D. Vigo, Neighborhood Search Algorithm for the Guillotine Non-Oriented Two-Dimensional Bin Packing Problem, Proceedings of the Meta-heuristics : Advances and Trends in Local Search Paradigms for Optimization, pp.125-139, 1997.
DOI : 10.1007/978-1-4615-5775-3_9

A. Lodi, S. Martello, and D. Vigo, Heuristic and Metaheuristic Approaches for a Class of Two-Dimensional Bin Packing Problems, INFORMS Journal on Computing, vol.11, issue.4, pp.345-357, 1999.
DOI : 10.1287/ijoc.11.4.345

B. S. Baker, E. G. Coffman-jr, and R. L. Rivest, Orthogonal packings in two dimensions Exact solution of the two-dimensional finite bin packing problem, SIAM Journal on Computing Management Science, vol.44, issue.3, pp.846-855, 1980.

K. Danne and S. Stuehmeier, OFF-LINE PLACEMENT OF TASKS ONTO RECONFIGURABLE HARDWARE CONSIDERING GEOMETRICAL TASK VARIANTS, From Specification to Embedded Systems Application of International Federation for Information Processing, 2005.
DOI : 10.1007/11523277_30

K. Bazargan, R. Kastner, and M. Sarrafzadeh, 3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246), pp.329-338, 2000.
DOI : 10.1109/IWRSP.1999.779029

S. P. Fekete, E. Kohler, and J. Teich, Optimal FPGA module placement with temporal precedence constraints, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.658-665, 2001.
DOI : 10.1109/DATE.2001.915093

J. Teich, S. P. Fekete, and J. Schepers, Optimization of dynamic hardware reconfigurations, The Journal of Supercomputing, vol.19, issue.1, pp.57-75, 2001.
DOI : 10.1023/A:1011188411132

F. Rivoallon and A. Cosoroaba, Achieving Higher System Performance with the Virtex 5 Family of FPGAs, Xilinx White Paper, 2006.

I. Belaid, F. Muller, and M. Benjemaa, Off-line placement of reconfigurable zones and off-line mapping of hardware tasks on FPGA, Proceedings of the Design and Architectures for Signal and Image Processing (DASIP '09), 2009.
URL : https://hal.archives-ouvertes.fr/hal-00524926

J. Clausen, Branch and Bound Algorithms-Principles and Examples, 1999.

G. Pataki, M. Tural, and E. B. Wong, Basis Reduction and the Complexity of Branch-and-Bound, Proceedings of the Annual ACM-SIAM Symposium on Discrete Algorithms, pp.1254-1261, 2010.
DOI : 10.1137/1.9781611973075.100

S. M. Azam, M. Ur-rehman, A. K. Bhatti, and N. Daudpota, Parallel branch and bound model using logarithmic sampling (PBLS) for symmetric traveling salesman problem, Proceedings of the World Academy of Science, Engineering and Technology, pp.66-69, 2005.

J. Hao, P. Galinier, and M. Habib, Métaheuristiques pour l'optimisation combinatoire et l'affectation sous contraintes, pp.283-324, 1999.

A. Neumaier, O. Shcherbina, W. Huyer, and T. Vinkóvink´vinkó, A comparison of complete global optimization solvers, Mathematical Programming, pp.335-356, 2005.
DOI : 10.1007/s10107-005-0585-4

J. A. Clemente, C. González, J. Resano, and D. Mozos, A hardware task-graph scheduler for reconfigurable multitasking systems, Proceedings of the International Conference on Reconfigurable Computing and FPGAs, pp.79-84, 2008.

L. Devaux, D. Chillet, S. Pillement, and D. Demigny, Flexible communication support for dynamically reconfigurable FPGAS, 2009 5th Southern Conference on Programmable Logic (SPL), pp.65-70, 2009.
DOI : 10.1109/SPL.2009.4914905

G. L. Djordjevi´cdjordjevi´c and M. B. To?i´to?i´c, A heuristic for scheduling task graphs with communication delays onto multiprocessors, pp.1197-1214, 1996.

J. A. Clemente, C. Gonzalez, J. Resano, and D. Mozos, A hardware task-graph scheduler for reconfigurable multitasking systems, Proceedings of the International Conference on Reconfigurable Computing and FPGAs, pp.79-84, 2008.

F. E. Sandnes and G. M. Megson, Improved Static Multiprocessor Scheduling using Cyclic Task Graphs: A Genetic Approach, Parallel Computing: Fundamentals, Applications and New Directions, pp.703-710, 1998.
DOI : 10.1016/S0927-5452(98)80092-0

Y. Abdeddaim, A. Kerbaa, and O. Maler, Task graph scheduling using timed automata, Proceedings International Parallel and Distributed Processing Symposium, p.237, 2003.
DOI : 10.1109/IPDPS.2003.1213431
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.15.6370

F. Redaelli, M. D. Santambrogio, and S. O. Memik, An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures, 2008 International Conference on Reconfigurable Computing and FPGAs, pp.97-102, 2008.
DOI : 10.1109/ReConFig.2008.42

Y. Yi, W. Han, X. Zhao, A. T. Erdogan, and T. Arslan, An ILP formulation for task mapping and scheduling on multi-core architectures, Proceedings of the Design, Automation and Test in Europe Conference (DATE '09), pp.33-38, 2009.

M. Huang, H. Simmler, P. Saha, and T. El-ghazawi, Hardware task scheduling optimizations for reconfigurable computing, 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, pp.1-10, 2008.
DOI : 10.1109/HPRCTA.2008.4745681

S. Fekete, E. Kohler, P. Saha, and J. Teich, Optimal FPGA module placement with temporal precedence constraints, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.658-665, 2001.
DOI : 10.1109/DATE.2001.915093

Z. Pan and B. E. Wells, Hardware supported task scheduling on dynamically reconfigurable SoC architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1465-1474, 2008.

W. H. Kohler, A Preliminary Evaluation of the Critical Path Method for Scheduling Tasks on Multiprocessor Systems, IEEE Transactions on Computers, vol.24, issue.12, pp.1235-1238, 1975.
DOI : 10.1109/T-C.1975.224171

K. Bazargan, R. Kastner, and M. Sarrafzadeh, Fast template placement for reconfigurable computing systems, IEEE Design & Test of Computers, vol.17, issue.1, pp.68-83, 2000.
DOI : 10.1109/54.825678

H. Elgindy, M. Middendorf, H. Schmeck, and B. Schmidt, Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer, Proceedings of the International Conference on Field Programmable Logic and Application, pp.379-388, 2000.
DOI : 10.1007/3-540-44614-1_41

A. Lodi, S. Martello, and M. Monaci, Two-dimensional packing problems: A survey, European Journal of Operational Research, vol.141, issue.2, pp.241-252, 2001.
DOI : 10.1016/S0377-2217(02)00123-6

A. Lodi, S. Martello, and D. Vigo, Neighborhood Search Algorithm for the Guillotine Non-Oriented Two-Dimensional Bin Packing Problem, Meta-Heuristics: Advances and Trends in Local Search Paradigms for Optimization, pp.125-139, 1997.
DOI : 10.1007/978-1-4615-5775-3_9

M. Panainte, K. Bertels, and S. Vassiliadis, FPGA-area allocation for partial run-time reconfiguration, Proceedings of the Design Automation Test Europe Conference (DATE '05), pp.100-105, 2005.

C. Kao, Benefits of Partial Reconfiguration, Xcell Journal, vol.55, pp.65-67, 2005.

K. Paulsson, M. H. ¨-ubner, S. Bayar, and J. Becker, Exploitation of Run-Time Partial Reconfiguration for Dynamic Power

S. Guccione, D. Levi, and P. Sundararajan, JBits: Java based interface for reconfigurable computing, 1999.

X. Inc, Virtex-5 Configuration User Guide, 2010.

K. Compton and S. Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys, vol.34, issue.2, pp.171-210, 2002.
DOI : 10.1145/508352.508353

R. Tessier and W. Burleson, Reconfigurable computing for digital signal processing: A survey, The Journal of VLSI Signal Processing, vol.28, issue.1/2, pp.7-27, 2001.
DOI : 10.1023/A:1008155020711

I. Belaid, F. Muller, and M. Benjemaa, New Three-level Resource Management Enhancing Quality of Off-line Hardware Task Placement on FPGA, International Journal of Reconfigurable Computing, pp.65-67, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00519278

J. A. Clemente, C. Gonzalez, J. Resano, and D. Mozos, A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems, 2008 International Conference on Reconfigurable Computing and FPGAs, pp.79-84, 2008.
DOI : 10.1109/ReConFig.2008.31

F. Redaelli, M. D. Santambrogio, and D. Sciuto, Task scheduling with configuration prefetching and antifragmentation techniques on dynamically reconfigurable systems, Proceedings of the conference on Design, automation and test in Europe, ser. DATE '08, pp.519-522, 2008.

B. Ouni, I. Belaid, F. Muller, and M. Benjemaa, Placement of Hardware Tasks on FPGA using the BEE Algorithm, International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS11), 2011.
URL : https://hal.archives-ouvertes.fr/hal-00662027

K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, and A. Thanailakis, DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation, 19th IEEE International Parallel and Distributed Processing Symposium, pp.165-165, 2005.
DOI : 10.1109/IPDPS.2005.158

D. Koch, C. Beckhoff, and J. Teich, Bitstream Decompression for High Speed FPGA Configuration from Slow Memories, 2007 International Conference on Field-Programmable Technology, pp.161-168, 2007.
DOI : 10.1109/FPT.2007.4439245
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.68.1862

P. Bomel, J. Crenne, L. Ye, J. Diguet, and G. Gogniat, Ultra-Fast Downloading of Partial Bitstreams through Ethernet, Proceedings of the 22nd International Conference on Architecture of Computing Systems, ser. ARCS '09, pp.72-83, 2009.
DOI : 10.1007/s11265-006-0017-6
URL : https://hal.archives-ouvertes.fr/hal-00488510

M. Liu, Z. Lu, W. Kuehn, and A. Jantsch, Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations, ReCoSoC, 2010.

K. Papadimitriou, A. Dollas, and S. Hauck, Performance of partial reconfiguration in FPGA systems, ACM Transactions on Reconfigurable Technology and Systems, vol.4, issue.4, 2010.
DOI : 10.1145/2068716.2068722

X. Inc, Partial Reconfiguration User Guide, p.100, 2010.

. Leuven, . Belgium, and . Belgium, European Design and Automation Association, pp.300-303, 2009.

A. Consortium, ARDMAHN project