SMART SAMPLING FOR RISK REDUCTION IN SEMICONDUCTOR MANUFACTURING

Abstract : In semiconductor manufacturing, several types of controls are required to ensure the quality of final products. In this thesis, we focus on defectivity inspections, which aim at monitoring the process for defect reduction and yield improvement. We are interested in managing and reducing the risk on process tools (i.e. number of wafers at risk) during fabrication. To reduce this risk, inspection operations are performed on products. However, because inspection operations directly impact the cycle times of products, sampling strategies are used to reduce the number of inspected lots while satisfying quality objectives. Several sampling techniques exist and can be classified according to their capability to deal with factory dynamics. Dynamic sampling strategies have recently been proposed, in which lots to inspect are selected in real time while considering the current production risk. These strategies are much more efficient than previous strategies but more complex to design and implement. In this thesis, a novel approach to select the lots to inspect is proposed. Multiple algorithms have been proposed and validated to efficiently manage the defect inspection queues by skipping (i.e. releasing) lots that do no longer bring enough information. In order to support strategic and tactical decisions, an optimization model for defect inspection capacity planning is also proposed. This model calculates the required defect inspection capacity to ensure the risk limits on process tools when the production conditions change. Industrial results show significant improvements in terms of risk reduction without increasing defect inspection capacity.
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Gloria Luz Rodriguez Verjan. SMART SAMPLING FOR RISK REDUCTION IN SEMICONDUCTOR MANUFACTURING. Other. Ecole Nationale Supérieure des Mines de Saint-Etienne, 2014. English. ⟨NNT : 2014EMSE0747⟩. ⟨tel-01126975⟩

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