A. A. Agarwal, C. Iskander, and R. Shankar, Outil de génération C.2 Outil de génération Figure C.6 ? Édition de la topologie, Survey of network on chip (NoC) architectures & contributions. Journal of engineering computing and architecture, 2009.

J. [. Ahonen and . Nurmi, Integration of a noc-based multimedia processing platform, International Conference on Field Programmable Logic and Applications, 2005., pp.606-611, 2005.
DOI : 10.1109/FPL.2005.1515796

A. [. Ahonen, H. Sigüenza-tortosa, J. Bin, and . Nurmi, Topology optimization for application-specific networks-on-chip, Proceedings of the 2004 international workshop on System level interconnect prediction , SLIP '04, pp.53-60, 2004.
DOI : 10.1145/966747.966758

. Bam-+-05-]-c, A. Bobda, M. Ahmadinia, J. Majer, S. Teich et al., Dy- NoC : A dynamic infrastructure for communication in dynamically reconfugurable devices, International Conference on Field Programmable Logic and Applications, pp.153-158, 2005.

L. [. Bertozzi and . Benini, Xpipes : a network-on-chip architecture for gigascale systems-on-chip. Circuits and Systems Magazine, IEEE, vol.4, issue.2, pp.18-31, 2004.

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture, vol.50, issue.2-3, pp.105-128, 2004.
DOI : 10.1016/j.sysarc.2003.07.004

]. L. Bhb-+-07, M. Braun, J. Hubner, T. Becker, V. Perschke et al., Circuit switched run-time adaptive network-on-chip for image processing applications, International Conference on Field Programmable Logic and Applications, pp.688-691, 2007.

]. D. Bjm-+-05, A. Bertozzi, S. Jalabert, R. Murali, S. Tamhankar et al., Noc synthesis flow for customized domain specific multiprocessor systems-on-chip, IEEE Transactions on Parallel and Distributed Systems, vol.16, issue.2, pp.113-129, 2005.

S. [. Bjerregaard and . Mahadevan, A survey of research and practices of networkon-chip, ACM Computing Surveys (CSUR), vol.38, issue.11, 2006.

J. [. Bjerregaard, . [. Sparso, J. Bjerregaard, and . Sparso, Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip A router architecture for connection-oriented service guarantees in the mango clockless network-on-chip, Norchip Conference Design, Automation and Test in Europe, pp.269-272, 2004.

[. Créput, R. Dafali, A. Rossi, and M. Sevaux, Communications reconfigurables dans un NoC : optimisation par approche évolutionnaire, 2010.

M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and A. Scandurra, Spidergon: a novel on-chip communication network, 2004 International Symposium on System-on-Chip, 2004. Proceedings., pp.15-20, 2004.
DOI : 10.1109/ISSOC.2004.1411133

G. Osso, L. Biccari, D. Giovannini, L. Bertozzi, . [. Benini et al., Xpipes : a latency insensitive parameterized network-on-chip architecture for multiprocessor socs The osi reference model, 21st International Conference on Computer Design Proceedings of the IEEE, pp.536-539, 1983.

J. [. Evain, . Ph, D. Diguet, and . Houzet, NoC design flow for TDMA and QoS management in a GALS context, EURASIP Journal on Embedded Systems, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00089589

A. [. Elmiligi, M. W. Morgan, F. El-kharashi, and . Gebali, A Topology-based Design Methodology for Networks-on-Chip Applications, 2007 2nd International Design and Test Workshop, pp.61-65, 2007.
DOI : 10.1109/IDT.2007.4437429

Y. Eustache, Reconfigurations Algorithmiques et Architectures Régulées : Contribution à l'Auto-Adaptation des Systèmes Embarqués, 2008.

D. [. Ford, . J. Fulkersonfly72-]-m, . [. Flynn, J. Goossens, A. Dielissen et al., Maximal flow through a network Some computer organizations and their effectiveness, Aethereal network on chip : concepts, architectures, and implementations. Design Test of Computers, pp.399-404948, 1956.

A. [. Guerrier and . Greiner, A generic architecture for on-chip packet-switched interconnections Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip, Design, Automation and Test in Europe Conference and Exhibition, pp.250-256, 2000.

S. [. Hecht, A. Kubisch, D. Herrholtz, and . Timmermann, Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs, International Conference on Field Programmable Logic and Applications, 2005., pp.527-530, 2005.
DOI : 10.1109/FPL.2005.1515777

R. [. Izu, C. Beivide, . [. Jesshope, R. Jingcao, . E. Marculescu-[-kczs01-]-m et al., Mad-postman : A look-ahead message propagation method for static bidimensional meshes Energy-and performance-aware mapping for regular noc architectures Communication architectures for system-on-chip Dynamic configuration for distributed systems The evolving philosophers problem : dynamic change management, Parallel and Distributed Processing Proceedings. Second Euromicro Workshop on 14th Symposium on Integrated Circuits and Systems Design, pp.117-124551, 1985.

]. A. Ler06 and . Leroy, Optimizing the on-chip communication architecture of low power Systemson-Chip in Deep Sub-Micron technology Link and N. Vijaykrishnan. Hotspot prevention through runtime reconfiguration in network-on-chip, pp.648-649, 2005.

T. Marescaux, B. Bricke, P. Debacker, V. Nollet, and H. Corporaal, Dynamic timeslot allocation for qos enabled networks on chip, 3rd Workshop on Embedded Systems for Real-Time MultimediaMC03] P. Moscato and C. Cotta. A gentle introduction to memetic algorithms. Handbook of metaheuristics, pp.47-52, 2003.

]. S. Mdm04a, G. Murali, and . Micheli, Bandwidth-constrained mapping of cores onto noc architectures, Design, Automation and Test in Europe Conference and Exhibition, pp.896-901, 2004.

]. S. Mdm04b, G. Murali, . De-micheli-[-mho05-]-r, J. Marculescu, U. Y. Hu et al., SUNMAP : a tool for automatic topology selection and generation for nocs Key research problems in noc design : a holistic perspective, Design Automation Conference Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Ni and P.K. McKinley. A survey of wormhole routing techniques in direct networks. Computer, pp.914-919, 1993.

. Nma-+-05-]-v, T. Nollet, P. Marescaux, D. Avasare, J. Verkest et al., Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles, pp.234-239, 2005.

T. [. Nollet, D. Marescaux, and . Verkest, Operating-system controlled network on chip, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.256-259, 2004.
DOI : 10.1145/996566.996637

R. [. Ogras, . Marculescupak06-]-t, C. Pionteck, R. Albrecht, and . Koch, Energy-and performance-driven noc communication architecture synthesis using a decomposition approach A dynamically reconfigurable packetswitched network-on-chip, Design, Automation and Test in Europe Design, Automation and Test in Europe, pp.352-357, 2005.

R. [. Pionteck, C. Koch, and . Albrecht, Applying partial reconfiguration to networks-on-chips Virtual shared memory : A survey of techniques and systems, International Conference on Field Programmable Logic and Applications, pp.1-6, 1992.

E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. Van-meerbergen et al., Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip, IEE Proceedings - Computers and Digital Techniques, vol.150, issue.5, pp.294-302, 2003.
DOI : 10.1049/ip-cdt:20030830

A. [. Salminen, T. D. Kulmala, and . Hamalainen, Survey of network-on-chip proposals . white paper, pp.1-13, 2008.

J. [. Stensgaard and . Sparso, ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), pp.55-64, 2008.
DOI : 10.1109/NOCS.2008.4492725

. Stm and . Stmicroelectronics, Stmicroelectronics unveils innovative networkon-chip technology for new system-on-chip interconnect paradigm

D. [. Wiklund and . Liu, SoCBUS: switched network on chip for hard real time embedded systems, Proceedings International Parallel and Distributed Processing Symposium, 2003.
DOI : 10.1109/IPDPS.2003.1213180

]. H. Zim80 and . Zimmermann, OSI reference model?the ISO model of architecture for open systems interconnection, Communications IEEE Transactions on, vol.28, issue.4, pp.425-432, 1980.

R. Liste-des-publications-chapitre-de-livre, J. Dafali, and . Diguet, Keys for Administration of Reconfigurable NoC Self-Adaptive Network Interface Case Study, Dynamic Reconfigurable Network-on-Chip Design : Innovations for Computational Processing and Communication, 2009.

C. , R. Dafali, and J. Diguet, MPSoC Architecture-Aware Automatic NoC Topology Design, IFIP International Conference on Network and Parallel Computing (NPC'10), 2010.
URL : https://hal.archives-ouvertes.fr/hal-01054961

R. Dafali and J. Diguet, Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager, 2009 International Conference on Reconfigurable Computing and FPGAs, 2009.
DOI : 10.1109/ReConFig.2009.62

URL : https://hal.archives-ouvertes.fr/hal-00446775

R. Dafali, J. Diguet, and M. Sevaux, Key Research Issues for Reconfigurable Networkon-Chip, ReConFig'08, International Conference on ReConFigurable Computing and FP- GAs, 2008.

R. Dafali, S. Evain, J. Diguet, and E. Juin, µSpider CAD tool : Case Study of NoC IP Generation for FPGA, DASIP'07, Workshop on Design and Architectures for Signal and Image Processing, 2007.