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Etude et implémentation d'une architecture de décodage générique et flexible pour codes correcteurs d'erreurs avancés

Jean Dion 1 
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Channel coding is a mathematical operation which improves the quality of the digital communication by correcting erroneous bits in reception. The usage constraints like a high quality reception, good throughputs, a small latency communication, a small silicon area or low power consumption promote the selection of a large variety of codes for standardized communication protocols. When industrial trend is to merge communication networks in order to answer a large panel of usage, the wide range of codes is a handicap to design a low cost transmitter. The media networks prefer advanced Forward Error Correction codes like turbo codes and LDPC codes to meet the constraints of signal quality. However, such an architecture has a huge hardware cost on the transmitter. A structure which fits to several kinds of codes and is able to adapt to an evolution of the medium protocol is not avoidable to design new usage scenarios.s This memory presents the principle of channel coding and several advanced forward error correction codes selected in the common standardized communication protocols. Common characteristics of QC-LDPC codes and turbo codes are underlined. The main algorithms and some decoding architectures are presented. The hardware complexity of the main decoding algorithms is estimated. They are compared for a given code with an equivalent correction capacity for QC-LDPC codes. A similar study is performed on the turbo codes. The decoding algorithms are then used to decode equivalent rate and length codes and laid out to achieve an equal correction capacity, in order to select a joint decoding algorithm fitting with the two families of code. The QC-LDPC codes and the turbo codes are structured thanks to a common trellis representation. The windowing technique commonly applied in turbo decoding is studied to decode a QC-LDPC code. Finally, the QC-LDPC interleaving are put in light and reconsidered in accordance with hardware constraints. A trellis decoding core compatible with 3GPP LTE and IEEE 802.11n standards is proposed. Several decoding structures are then introduced incorporating one or several cores. The integration on a FPGA target is detailed. A use-case scenario with a decoding context evolving every received message is proposed and highlights the impact of the reconfiguration on throughputs. The multi-standard structure requires 4.2 % (respectively 5.3 %) additive hardware resources in comparison with a single standard one compatible with 3GPP LTE (resp. IEEE 802.11n). The reconfiguration between two codewords from different standards reduces the throughputs by less than 1 %. A multi-cores architecture is also brought on a 65 nm ASIC target. This architecture operates at a frequency of 500 MHz on a 2.1 mm2 silicon area, decoding codewords from 3GPP LTE and IEEE 802.11n standards, and accepting a dynamic reconfiguration between two consecutive codewords.
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Submitted on : Wednesday, March 19, 2014 - 11:10:50 AM
Last modification on : Thursday, October 27, 2022 - 3:45:16 PM
Long-term archiving on: : Thursday, June 19, 2014 - 11:23:59 AM


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Jean Dion. Etude et implémentation d'une architecture de décodage générique et flexible pour codes correcteurs d'erreurs avancés. Théorie de l'information et codage [math.IT]. Télécom Bretagne, Université de Bretagne Occidentale, 2013. Français. ⟨NNT : ⟩. ⟨tel-00960978⟩



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