Recherche opérationnelle et optimisation pour la conception testable de circuits intégrés complexes

Lilia Zaourar 1
1 G-SCOP_ROSP - ROSP
G-SCOP - Laboratoire des sciences pour la conception, l'optimisation et la production
Abstract : This thesis is a research contribution interfacing operations research and microelectronics. It consid ers the use of combinatorial optimization techniques for DFT ( Design For Test ) of Integrated Circuits ( IC ). With the growing complexity of current IC both quality and cost during manufacturing testing have become important parameters in the semiconductor industry. To ensure proper functioning of the IC , the testing step is more than ever a crucial and difficult step in the overall IC manufacturing process. To answer market requirements, chip testing should be fast and effective in uncove ring defects. For this, it becomes essential to app rehend the test phase from the design steps of IC . In this context, DFT techniques and methodologies aim at improving the testability of IC . In previous research works, several problems of opt imization and decision making were derived from the micro- electronics domain. Most of previous research contr ibutions dealt with problems of combinatorial optim ization for placement and routing during IC design. In this the sis, a higher design level is considered where the DFT problem is analyzed at the Register Transfer Level (RTL) before the logic synt hesis process starts. This thesis is structured into three parts. In the first part, preliminaries and basic concepts of operations research, IC design and manufacturing are introduced. Next, both our approach and the solutio n tools which are used in the rest of this work are presented. In the second part, the problem of optimizing the i nsertion of scan chains is considered. Currently, " internal scan" is a widely adopted DFT technique for sequential di gital designs where the design flip-flops are conne cted into a daisy chain manner with a full controllability and observability from primary inputs and outputs. In this part of the research work, different algorithms are developed t o provide an automated and optimal solution during the generation of an RTL scan architecture where severa l parameters are considered: area, test time and po wer consumption in full compliance with functional perf ormance. This problem has been modelled as the sear ch for short chains in a weighted graph. The solution meth ods used are based on finding minimal length Hamilt onian chains. This work was accomplished in collaboration with DeFacTo Technologies, an EDA start-up close to Grenoble. The third part deals with the problem of sharing BIST ( Built In Self Test ) blocks for testing memories. The problem can be formulated as follows: given the memories wi th various types and sizes, and sharing rules for s eries and parallel wrappers, we have to identify solutions to the problem by associating a wrapper with each mem ory. The solution should minimize the surface, the power con sumption and test time of IC . To solve this problem, we designed a prototype called Memory BIST Optimizer ( MBO ). It consists of two steps of resolution and a val idation phase. The first step creates groups of compatibili ty in accordance with the rules of abstraction and sharing that depend on technologies. The second phase uses genet ic algorithms for multi-objective optimization in o rder to obtain a set of non dominated solutions. Finally, the validation verifies that t he solution provided is valid. In addition, it displays all solutions through a graph ical or textual interface. This allows the user to choose the solution that fits best. The tool MBO is currently integrated into an industrial flow wi thin ST-microelectronics .
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Lilia Zaourar. Recherche opérationnelle et optimisation pour la conception testable de circuits intégrés complexes. Recherche opérationnelle [cs.RO]. Université Joseph-Fourier - Grenoble I, 2010. Français. ⟨tel-00959786⟩

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