A. Lesellier, O. Jamin, J. Bercher, and E. O. Venard, Etude d'architectures de numérisation très large bande, MajecSTIC 2010, p.8, 2010.

A. Lesellier, O. Jamin, J. Bercher, and E. O. Venard, Broadband digitization for cable tuners front-end, 41st European Microwave Conference (EuMC), pp.705-708, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00766468

A. Lesellier, O. Jamin, J. Bercher, and E. O. Venard, Design, optimization and calibration of an HFB-based ADC, 2011 IEEE 9th International New Circuits and systems conference, pp.317-320, 2011.
DOI : 10.1109/NEWCAS.2011.5981319
URL : https://hal.archives-ouvertes.fr/hal-00766542

A. Lesellier, O. Jamin, J. Bercher, and E. O. Venard, Design, optimization and realization of an HFB-based ADC, 2011 20th European Conference on Circuit Theory and Design (ECCTD), pp.138-141, 2011.
DOI : 10.1109/ECCTD.2011.6043296
URL : https://hal.archives-ouvertes.fr/hal-00766464

J. Mitola, The software radio architecture, IEEE Communications Magazine, vol.33, issue.5, pp.26-37, 1995.
DOI : 10.1109/35.393001

J. Mitola and G. Maguire, Cognitive radio: making software radios more personal, IEEE Personal Communications, vol.6, issue.4, pp.13-18, 1999.
DOI : 10.1109/98.788210

F. Lang, A 6 bit 25 GS/s flash interpolating ADC in 90 nm CMOS technology, 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, pp.117-120, 2011.
DOI : 10.1109/PRIME.2011.5966231

D. Ferenci, A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology, Microwave Integrated Circuits Conference (EuMIC), 2010 European (presented at the Microwave Integrated Circuits Conference (EuMIC), pp.214-217, 2010.

V. Hiremath and S. Ren, A 6-bit low power folding and interpolating ADC, 2011 IEEE International Instrumentation and Measurement Technology Conference, pp.1-6, 2011.
DOI : 10.1109/IMTC.2011.5944164

M. Kwon, A digitally self-calibrated low-noise 7-bit folding A/D converter, 23rd IEEE International SOC Conference, pp.39-43, 2010.
DOI : 10.1109/SOCC.2010.5784637

M. Miyahara, A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC, 2011 Symposium on VLSI Circuits (VLSIC) (presented at the 2011 Symposium on VLSI Circuits (VLSIC), pp.126-127, 2011.

M. R. , A. , and M. Yavari, A 10-bit 250MS/s pipelined ADC with a merged S/H & 1st stage using an optimal opamp sharing technique, 19th Iranian Conference on Electrical Engineering (ICEE) (presented at the 2011 19th Iranian Conference on Electrical Engineering (ICEE), pp.1-1, 2011.

S. Cho, A 550-<formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{W}$</tex> </formula> 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction, IEEE Journal of Solid-State Circuits, vol.46, issue.8, pp.1881-1892, 2011.
DOI : 10.1109/JSSC.2011.2151450

M. Yoshioka, A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration, " in Solid-State Circuits Conference Digest of Technical Papers, 2010 IEEE International (presented at the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.384-385, 2010.

C. Lee and M. P. Flynn, A 14 b 23 MS/s 48 mW Resetting <formula formulatype="inline"> <tex Notation="TeX">$\Sigma \Delta$</tex></formula> ADC, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, issue.6, pp.1167-1177, 2011.
DOI : 10.1109/TCSI.2010.2097716

W. Lei, A 14-b 2MSPS Low Power Sigma-Delta ADC Using Feed-Forward Structure, 2011 Third International Conference on Measuring Technology and Mechatronics Automation, pp.3-5, 2011.
DOI : 10.1109/ICMTMA.2011.7

I. Galton and H. T. Jensen, Oversampling parallel delta-sigma modulator A/D conversion, IEEE Transactions on Circuits and Systems-II : Analog and Digital Signal Processing, pp.801-810, 1996.
DOI : 10.1109/82.553396

A. Eshraghi and T. S. Fiez, A Comparative Analysis of Parallel Delta???Sigma ADC Architectures, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, issue.3, pp.450-458, 2004.
DOI : 10.1109/TCSI.2004.823663

A. Beydoun, Système de numérisation hautes performances à base de modulateurs sigma-delta passe-bande, Ph.D. Diss., Supélec, vol.11, 2008.

W. C. Black and D. A. Hodges, Time interleaved converter arrays, IEEE Journal on Solid-State Circuits, issue.6, pp.1022-1029, 1980.
DOI : 10.1109/isscc.1980.1156111

K. Poulton, J. J. Corcoran, and T. Hornak, A 1-GHz 6-bit ADC system, IEEE Journal of Solid-State Circuits, vol.22, issue.6, pp.1781-1789, 1987.
DOI : 10.1109/JSSC.1987.1052844

Y. C. Jenq, Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving, IEEE Transactions on Instrumentation and Measurement, vol.39, issue.1, pp.71-75, 1990.
DOI : 10.1109/19.50419

H. Jin and K. F. Lee, A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs, IEEE Transactions on Circuits and Systems II, vol.47, issue.7, pp.603-613, 2000.

K. Doris, A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist, 2011 IEEE International Solid-State Circuits Conference, pp.180-182, 2011.
DOI : 10.1109/ISSCC.2011.5746272

A. Petraglia and S. K. Mitra, High-speed A/D conversion incorporating a QMF bank, IEEE Transactions on Instrumentation and Measurement, vol.41, issue.3, pp.427-431, 1992.
DOI : 10.1109/19.153341

A. Petraglia and M. A. Pinheiro, Effects of quantization noise in parallel arrays of analog-to-digital converters, Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS '94, pp.337-340, 1994.
DOI : 10.1109/ISCAS.1994.409375

M. A. Pinheiro, P. B. Batalheiro, A. Petraglia, and M. R. Petraglia, Improving the near-perfect hybrid filter bank performance in the presence of realization errors, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), pp.1069-1072, 2001.
DOI : 10.1109/ICASSP.2001.941104

M. A. Pinheiro and A. Petraglia, On the performance of discrete-time hybrid filter banks with coefficient errors and arma stochastic process input, Proceedings of IEEE International Symposium on Circuits and Systems, pp.521-524, 2004.

P. P. Vaidyanathan, Multirate Systems and Filter Banks, 1993.

P. Löwenborg, Analysis and Synthesis of Asymmetric Filter Banks with Application to Analog-to-Digital Conversion, 2001.

P. Löwenborg, H. Johansson, and L. Wanhammar, On the frequency response of Mchannel mixed analog and digital maximally decimated filter banks, Proceedings of European Conference on Circuit Theory and Design, pp.321-324, 1999.

S. R. Velazquez, Hybrid filter banks for analog/digital conversion, 1997.
DOI : 10.1109/78.668549
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.18.3193

P. Löwenborg, H. Johansson, and L. Wanhammar, A class of two-channel hybrid analog/digital filter banks, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), pp.14-17, 1999.
DOI : 10.1109/MWSCAS.1999.867197

P. Löwenborg, H. Johansson, and L. Wanhammar, A class of two-channel approximately perfect reconstruction hybrid analog/digital filter banks, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), pp.579-582, 2000.
DOI : 10.1109/ISCAS.2000.857161

P. Löwenborg, H. Johansson, and L. Wanhammar, A class of two-channel hybrid analog/digital filter banks, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), 2000.
DOI : 10.1109/MWSCAS.1999.867197

P. Löwenborg, H. Johansson, and L. Wanhammar, A two-channel hybrid analog and IIR filter bank approximating perfect magnitude reconstruction, Proceedings of IEEE Nordic Signal Processing Symposium, 2000.

P. Löwenborg, H. Johansson, and L. Wanhammar, Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, issue.7, pp.355-367, 2003.
DOI : 10.1109/TCSII.2003.813589

H. Shu, T. Chen, and B. A. Francis, MinMax design of hybrid multirate filter banks, IEEE Transactions on Circuits and Systems-II : Analog and Digital Signal Processing, pp.120-128, 1997.

S. R. Velazquez, T. Q. Nguyen, S. R. Broadstone, and J. K. Roberge, A hybrid filter bank approach to analog-to-digital conversion, Proceedings of IEEE-SP International Symposium on Time- Frequency and Time-Scale Analysis, pp.116-119, 1994.
DOI : 10.1109/TFSA.1994.467350

O. Oliaei, Asymptotically perfect reconstruction in hybrid filter banks, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181), pp.1829-1832, 1998.
DOI : 10.1109/ICASSP.1998.681818

O. Oliaei, High-speed A/D and D/A converters using hybrid filter banks, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), pp.143-146, 1998.
DOI : 10.1109/ICECS.1998.813289

P. Löwenborg, H. Johansson, and L. Wanhammar, Analysis of gain and timeskew errors in filter bank based A/D converters, Proceedings of IEEE Midwest Symposium on Circuits and Systems, 2001.

S. R. Velazquez, Hybrid filter bank analog/digital converter, 1996.
DOI : 10.1109/tfsa.1994.467350

S. R. Velazquez, Parallel processing analog and digital converter, Patent No: US 6177893, 2001.

S. R. Velazquez, Adaptive parallel processing analog and digital converter, Patent No: US 6339390 B1, 2002.

C. Lelandais-perrault, D. Poulton, and J. Oksman, Synthesis of hybrid filter banks for A/D conversion with implementation constraints -direct approach-, 2003 46th Midwest Symposium on Circuits and Systems, 2003.
DOI : 10.1109/MWSCAS.2003.1562231

C. Lelandais-perrault, D. Poulton, and J. Oksman, Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolution, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., pp.51-54, 2005.
DOI : 10.1109/ECCTD.2005.1522907

C. Lelandais-perrault, D. Silion, T. Petrescu, and D. Poulton, Hybrid filter banks A/D converters using IIR synthesis filters, 48th Midwest Symposium on Circuits and Systems, 2005., 2005.
DOI : 10.1109/MWSCAS.2005.1594402

T. Petrescu, C. Lelandais-perrault, and J. Oksman, Synthesis of hybrid filter banks for A/D conversion with implementation constraints - mixed distortion/aliasing optimization $, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.997-1000, 2004.
DOI : 10.1109/ICASSP.2004.1326428

T. Petrescu and J. Oksman, Synthesis of hybrid filter banks for A/D conversion with implementation constraints -optimized frequency response approach -, 2003 46th Midwest Symposium on Circuits and Systems, 2003.
DOI : 10.1109/MWSCAS.2003.1562273

T. Petrescu, J. Oksman, and P. Duhamel, Synthesis of Hybrid Filter Banks by Global Frequency Domain Least Square Solving, 2005 IEEE International Symposium on Circuits and Systems, 2005.
DOI : 10.1109/ISCAS.2005.1465898

C. Lelandais-perrault, Systèmes de numérisation hautes performances ? Etude des solutions à bancs de filtres hybrides ? Extension des fonctionnalités, 2006.

R. Vaughan, N. Scott, and E. D. White, The theory of bandpass sampling, IEEE Transactions on Signal Processing, vol.39, issue.9, pp.1973-1984, 1991.
DOI : 10.1109/78.134430

S. Yu and X. Wang, Bandpass Sampling of One RF Signal Over Multiple RF Signals With Contiguous Spectrums, Signal Processing Letters, vol.16, pp.14-17, 2009.

J. Li, X. Zeng, L. Xie-chen, J. Zhang, and Y. Guo, A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications Solid-State Circuits, IEEE Journal, vol.43, pp.321-329, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00950004

A. Ismail and M. Elmasry, A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology Solid-State Circuits, IEEE Journal, vol.43, pp.1982-1990, 2008.

B. P. Ginsburg and A. P. Chandrakasan, Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver Solid-State Circuits, IEEE Journal, vol.42, pp.247-257, 2007.

. Byung-geun-lee, G. Byung-moo-min, E. J. Manganaro, and . Valvano, A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC Solid-State Circuits, IEEE Journal, vol.43, pp.2613-2619, 2008.

Y. Yao, F. Dai, J. Irwin, and E. R. Jaeger, A 3-Bit 2.2V 3.08pJ/conversion-step 11GS/s flash ADC in a 0.12?m SiGe BiCMOS technology, Bipolar/BiCMOS Circuits and Technology Meeting, pp.256-259, 2008.

A. Agnes, E. Bonizzoni, P. Malcovati, and E. F. Maloberti, A 9.4-ENOB 1V 3.8?W 100kS/s SAR ADC with Time-Domain Comparator Solid-State Circuits Conference, Digest of Technical Papers. IEEE International, pp.246-610, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00087033

Y. Park, S. Hwang, and M. Song, A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder, pp.51-54, 2005.

C. Hsu, A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS, 2007 IEEE Symposium on VLSI Circuits, pp.66-67, 2007.
DOI : 10.1109/VLSIC.2007.4342768

S. M. Louwsma, A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS Solid-State Circuits, IEEE Journal, vol.43, issue.4, pp.778-786, 2008.

D. Asemani and J. Oksman, Influences of oversampling and analog imperfections on Hybrid Filter Bank AD Converters, Symposium MWSCAS '06, pp.123-126, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00261344

S. R. Velazquez, T. Q. Nguyen, and S. R. Broadstone, Design of hybrid filter banks for analog/digital conversion, IEEE Transactions on Signal Processing, vol.46, issue.4, pp.956-967, 1998.
DOI : 10.1109/78.668549

P. Lowenborg, H. Johansson, and L. Wanhammar, A design procedure for 2-channel mixed analog and digital banks for AD conversion using minimax optimization, Proc ICECS'99, pp.1189-1192, 1999.

P. Lowenborg, H. Johansson, and L. Wanhammar, A class of two-channel hybrid analog/digital filter banks, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), pp.14-17, 1999.
DOI : 10.1109/MWSCAS.1999.867197

L. Zhiyu and L. Maoliu, Design of two-channel hybrid analog/digital banks satisfying near-perfect reconstruction, Proceedings 7th International Conference on Signal Processing, 2004. Proceedings. ICSP '04. 2004., pp.407-410, 2004.
DOI : 10.1109/ICOSP.2004.1452668

R. Koilpillai and P. Vaidyanathan, Cosine-modulated FIR filter banks satisfying perfect reconstruction, IEEE Transactions on Signal Processing, vol.40, issue.4, pp.770-783, 1992.
DOI : 10.1109/78.127951

T. Petrescu and J. Oksman, Sensitivity of hybrid filter banks AD converters to analog realization errors and finite word length, Proc ICASSP'06, pp.361-364, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00261350

A. I. Zverev, Handbook of Filter Synthesis, 1967.

J. Kaukovuori, K. Stadius, J. Ryynanen, and E. K. Halonen, Analysis and Design of Passive Polyphase Filters Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.55, pp.3023-3037, 2008.

E. Cetin, I. Kale, and E. R. Morling, Adaptive self-calibrating image rejection receiver, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577), pp.2731-2735, 2004.
DOI : 10.1109/ICC.2004.1313027
URL : http://westminsterresearch.wmin.ac.uk/923/1/Cetin_Izzet_Morling_2004_final.pdf

M. A. Enderwitz, R. A. Elliot, F. Darbari, L. H. Crockett, S. Weiss et al., Digital RF multiplexing for a TVWS transceiver implementation, URSI UK Festival of Radio Science, 2012.

R. A. Elliot, M. A. Enderwitz, F. Darbari, L. H. Crockett, S. Weiss et al., Efficient TV white space filter bank transceiver, 2012.

A. Kammoun, C. Lelandais-perrault, and M. Debbah, SNR efficient approach for the design of Hybrid Filter Bank A/D converters, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing
DOI : 10.1109/ICASSP.2013.6638150
URL : https://hal.archives-ouvertes.fr/hal-00862740