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System-Level Power Estimation Methodology for MPSoC based Platforms

Abstract : Shifting the design entry point up to the system-level is the most important countermeasure adopted to manage the increasing complexity of Multiprocessor System on Chip (MPSoC). The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of power and energy efficiency. However, taking decisions at this level is very difficult, since the design space is extremely wide and it has so far been mostly a manual activity. Efficient system-level power estimation tools are therefore necessary to enable proper Design Space Exploration (DSE) based on power/energy and timing.
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  • HAL Id : tel-00943272, version 1

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Santhosh Kumar Rethinagiri. System-Level Power Estimation Methodology for MPSoC based Platforms. Other. Université de Valenciennes et du Hainaut-Cambresis, 2013. English. ⟨NNT : 2013VALE0006⟩. ⟨tel-00943272⟩

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