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Optimisation des transferts de données sur systèmes multiprocesseurs sur puce

Abstract : Multiprocessor system on chip (MPSoC) such as the CELL processor or the more recent Platform2012 are heterogeneous multi-core architectures, with a powerful host processor and a computation fabric, consisting of several smaller cores, whose intended role is to act as a general purpose programmable accelerator. Therefore computation-intensive (and parallelizable) parts of the application initially intended to be executed by the host processor are offloaded to the multi-cores for execution. These parts of the application are often data intensive, operating on large arrays of data initially stored in a remote off-chip memory whose access time is about 100 times slower than that of the cores local memory. Accessing data in the off-chip memory becomes then a main bottleneck for performance. A major characteristic of these platforms is a software controlled local memory storage rather than a hidden cache mechanism where data movement in the memory hierarchy, typically performed using a DMA (Direct Memory Access) engine, are explicitely managed by the software. In this thesis, we attempt to optimize such data transfers in order to reduce/hide the off-chip memory latency.
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Submitted on : Tuesday, October 22, 2013 - 12:52:07 PM
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Selma Saidi. Optimisation des transferts de données sur systèmes multiprocesseurs sur puce. Autre [cs.OH]. Université de Grenoble, 2012. Français. ⟨NNT : 2012GRENM099⟩. ⟨tel-00875582⟩



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