A 0.21m 1.8V SOI 550MHz 64b Power PC Microprocessor with copper Interconnects " International Solid-State Circuits Conference, pp.438-439, 1999. ,
Characterization and modeling of capacitances in FD-SOI devices ,
New parameter extraction method based on split C-V for FDSOI MOSFETs, Essderc, 2012. ,
Threshold voltage and C- V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers Electron Devices Volume: 39 , Issue: 10 Page(s): Analysis of the gatesource/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation " Electron Devices Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below " Semiconductor Manufacturing, IEEE Transactions on IEEE Transactions on IEEE Transactions on, vol.53, issue.21, pp.2346-2353, 1992. ,
[FLEXpde] Ce logiciel à usage général permet d'obtenir des solutions numériques aux équations aux dérivées partielles en 2 ou 3 dimensions. Il est basé sur la méthode des éléments finis, pp.504-512, 2008. ,
Improved Method for the oxide thickness extraction in MOS structures with ultrathin gate dielectrics, Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices with Gate-source, 2000. ,
Electron Devices, IEEE Transactions on, vol.53, p.9 ,
Comprehensive and Accurate Parasitic Capacitance Models for Two-and Three-Dimensional CMOS Device Structures Saturation capacitance of thin oxide MOS structures and the effective surface density of states of silicon " Solid- State Electronics Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs, Semiconductor-On-Insulator Materials for Nanoelectronics Applications Improved split C?V method for effective mobility extraction in sub-0.1 µm Si MOSFETs " . IEEE Electron Dev Lett, pp.2143-2150, 1974. ,
Partially-Depleted SOI Technology for Digital Logic " IEEE International Solid-State Circuits Conference, 1999. ,
A simple model for the overlap capacitance of a VLSI MOS device " Electron Devices Issue: 12 Page(s): Parasitic capacitance of sub micrometer MOSFET's Verification of overlap and fringing capacitance models for MOSFET's " Solid-State Electron, IBM Journal of Research and Development Page IEEE Transactions on IEEE Trans. Electron Devices, vol.121, issue.44, pp.1870-1875, 1982. ,
In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs Electron Device Letters Issue: 10 Page(s): Enhanced performance in 50 nm N-MOSFETs with siliconcarbon source/drain regions " in IEDM Tech. Dig Concentration dependence of drift and magneto resistance ballistic mobility in a scaled-down metal oxide semiconductor field-effect transistor Solid State Physics, IEEE Applied Physics Letters, vol.99, pp.26755-757, 1976. ,
An investigation of steady-state velocity overshoot in silicon, Solid-State Electronics, vol.28, issue.4, pp.407-413, 1970. ,
DOI : 10.1016/0038-1101(85)90100-5
Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology, VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on Page, pp.1-2 ,
Comparison of carrier velocity gain in uniaxially and biaxially strained N-MOSFETs, Electronics Letters, vol.43, p.647, 2007. ,
Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters, IEEE Transactions on Electron Devices, vol.53, issue.4, pp.759-68, 2006. ,
DOI : 10.1109/TED.2006.870888
Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS " in VLSI Symp Electron mobility behavior in extremely thin SOI MOSFETS, Tech. Dig. IEEE Electron Device Letters, vol.16, pp.180-181, 1995. ,
Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling, 2006. ,
URL : https://hal.archives-ouvertes.fr/hal-00147133
Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation " Solid-State Electronics, 2004. ,
Study of low field electron transport in ultra-thin single and double-gate SOI MOSFETs " Electron Devices Meeting, pp.719-722, 2002. ,
Linear combination of bulk bands method for investigating the low-dimensional electron gas in nanostructured devices Neutral Impurity Scattering in Semiconductors Ultra Compact FDSOI Transistors including Strain and Orientation: Processing and Performance, Phys. Rev. B Physical Review ECS Trans, vol.72, issue.4, pp.14-1013, 1950. ,
UTBOX and ground plane combined with Al 2 O 3 inserted in TiN gate for V T modulation in fully-depleted SOI CMOS transistors, International Symposium on VLSI Technology, Systems and Applications -VLSI-TSA, pp.1-2, 2011. ,
Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates VLSI Technology (VLSIT),Symposium on Page(s): New experimental insight into ballisticity of transport in strained bulk MOSFETs, Symposium on VLSI Technology Digest, pp.115-116, 2009. ,
Effects of surface roughness in inversion layer transport " IEDM Tech, pp.605-613, 1984. ,
Physique de l'état solide " édition DUNOD A review of some charge transport properties of silicon MOSFET electron inversion layer motilities A physically based semi-empirical model for a wide temperature range, Hong05] Hong-Nien Lin et al " Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs " Electron Device Letters, pp.77-89, 1977. ,
Symmetrical 45nm PMOS on [110] substrate with excellent S/D extension distribution and mobility enhancement " VLSI Technology Digest of Technical Papers Intrinsic Origin of Electric Dipoles Formed at High- k/SiO2 Interface Elementary scattering theory of the Si MOSFET, Symposium IEDM IEEE Electron Device Lett, vol.18, issue.7, pp.9-676, 1997. ,
Essential physics of carrier transport in nanoscale MOSFETs, IEEE Transactions on Electron Devices, vol.49, issue.1, pp.133-141, 2002. ,
DOI : 10.1109/16.974760
On the mobility versus drain current relation for a nanoscale MOSFET, IEEE Electron Device Letters, vol.22, issue.6, pp.293-298, 2001. ,
Fundamentals of carrier transport, 2006. ,
DOI : 10.1017/CBO9780511618611
Physique des semiconducteurs et des composants électroniques Modeling of carrier mobility against carrier concentration in arsenic, phosphorus, and boron-doped silicon, édition Dunod IEEE Transactions on Electron Devices, vol.30, issue.7, pp.764-773, 1983. ,
Ballistic metal-oxide semiconductor field effect transistor High-mobility p-channel metaloxide-semiconductor field-effect transistor on strained Si, Journal of Applied Physics Applied Physics Letters, vol.76, issue.62 22, pp.48792853-2855, 1993. ,
Fully Quantum Self-Consistent Study of Ultimate DG-MOSFETs Including Realistic E5 Scattering Using a Wigner Monte-Carlo Approach " IEDM Technical Digest, pp.941-944, 2006. ,
In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), [110, Electron Devices Meeting,. IEDM Technical Digest. IEEE International, issue.111, pp.225-228, 2004. ,
New magneto resistance method for mobility extraction in scaled fully-depleted SOI devices " Pages 153 ? SOI Conference, Proceedings.IEEE International, 2004. ,
Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors " in IEDM Tech New method for the extraction of MOSFET parameters, Microelectronic Engineering Dig. Electronics Letters, vol.8024, issue.17 9, pp.241-244, 1988. ,
In Situ Comparison of Si/High-k and Channel Properties in SOI MOSFETs, IEEE Electron Device Lett, vol.30, issue.10, p.232, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00596074
Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs Solid-State Electronics Pages 123?130 Assessment of the impact of biaxial strain on the drain current of decanometric n-MOSFET, Solid-State Device Research Conference, pp.5-166, 2006. ,
Characterization and modeling of back bias on remote-Coulomb-limited mobility in UTBB-FDSOI Devices, 2012. ,
Explaining the dependences of the hole and electron motilities in Si inversion layers, IEEE Transactions on Electron Devices, vol.47, issue.4, pp.718-742, 2000. ,
Energy-band structure in strained silicon: A 20-band kp and Bir?Pikus Hamiltonian model The scattering of electrons by surface oxide charge and by the lattice vibrations at the Si-SiO2 interface SOI MOSFETs effective channel mobility, Roma04] K. Romanjek et al, WOLTE proceedings, pp.1795-201, 1972. ,
Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement Low ballistic mobility in submicron HEMTs, IEDM Tech. DigSmit54] C. S. Smith " Piezoresistance effect in Germanium and Silicon, pp.433-436, 1954. ,
Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode applications " European Solid-State Device Research On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration, ESSDERC 33rd Conference on Electron Devices, pp.2357-2362, 1994. ,
Intrinsic Correlation between Mobility Reduction and V T shift due to Interface Dipole Modulation in HfSiON/SiO 2 stack by La or Al addition Experimental Study on the Universality of Mobility Behavior in Ultra Thin Body Metal Oxide Semiconductor Field Effect Transistors Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime " IEDM technical digest Experimental determination of mobility scattering mechanisms in Si, Electron Devices Meeting IEDM Technical Digest. IEEE International, pp.3889-3892, 2004. ,
Ballistic transport in high electron mobility transistors, IEEE Transactions on Electron Devices, vol.50, issue.7, 2003. ,
DOI : 10.1109/TED.2003.814980
Accurate Investigation of the High-k Soft Phonon Scattering Mechanism in Metal Gate MOSFETs, Proceedings of ESSDERC, pp.379-382, 2005. ,
On the mobility in high-k/metal gate MOSFETs : Evaluation of the high-k phonon scattering impact Strain dependence of the performance enhancement in strained-Si n-MOSFETs, Scaling the Si MOSFET: from bulk to SOI to bulk " Electron Devices, pp.626-657, 1994. ,
High performance CMOS fabricated on hybrid substrate with different crystal orientations, IEEE International Electron Devices Meeting 2003, pp.1704-1710, 1992. ,
DOI : 10.1109/IEDM.2003.1269320
On the Apparent Mobility in Nanometric n-MOSFETs, IEEE Electron Device Letters, vol.28, issue.11, 2003. ,
DOI : 10.1109/LED.2007.907553
Comprehensive understanding of surface roughness and Coulomb scattering mobility in ,
Characterization and Modeling of Capacitances in FD-SOI Devices " I, Cork, vol.2, 2011. ,
Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical and mobility performances " I Impact of 45° rotated substrate on UTBOX FDSOI high-k Metal gate technology " I, Boeuf EuroSOI 2012 Montpellier 4 ,
Boeuf VLSI TSA 2012 Taiwan 6 New split C-V based parameter extraction method for FDSOI MOSFETs " I, Essderc 2012 Bordeau 7. " On the understanding of mobility degradation mechanisms in advanced CMOS devices: FDSOI versus bulk technology " I.Ben-Akkez C.Diouf A. Cros C.Fenouillet-Beranger ,
Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates, 2012 Symposium on VLSI Technology (VLSIT) ,
DOI : 10.1109/VLSIT.2012.6242488
2012 Symposium on 9 Characterization and Modeling of Back Bias Impacts on Remote-Coulomb-Limited Mobility in UTBB-FDSOI Devices ,