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Evaluation of power management strategies on actual multiprocessor platforms

Abstract : The purpose of this study is to investigate how power management strategies can be efficiently exploited in actual platforms. Primarily, the challenges in multicore based embedded systems lies in managing the energy expenditure, determining the scheduling behavior and establishing methods to monitor power and energy, so as to meet the demands of the battery life and load requirements. The work presented in this dissertation is a study of low power-aware strategies in the practical world for single and multiprocessor platforms. The approach used for this study is based on representative multiprocessor platforms (real or virtual) to identify the most influential parameters, at hardware as well as application level, unlike many existing works in which these parameters are often underestimated or sometimes even ignored. The work analyzes and compares in detail various experimentations with different power policies based on Dynamic Voltage and Frequency Scaling (DVFS) and Dynamic Power Switching (DPS) techniques, and investigates the conditions at which these policies are effective in terms of energy savings. The results of these investigations reveal many interesting and notable conclusions that can serve as prerequisites for the efficient use of power management strategies. This work also shows the potential of advanced domain specific power strategies compared to real world available strategies that are general purpose based in their majority. Finally, some high level consumption models are derived from the different energy measurement results to let the estimation of power management benefits at early stages of a system development.
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Submitted on : Wednesday, June 26, 2013 - 3:49:29 PM
Last modification on : Thursday, August 4, 2022 - 4:56:48 PM
Long-term archiving on: : Friday, September 27, 2013 - 4:30:19 AM


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  • HAL Id : tel-00838799, version 1



Jabran Khan Jadoon. Evaluation of power management strategies on actual multiprocessor platforms. Hardware Architecture [cs.AR]. Université Nice Sophia Antipolis, 2013. English. ⟨NNT : 2013NICE4012⟩. ⟨tel-00838799⟩



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