.. Et and S. , 24 1.2.1 Evolution des mémoires DRAM, Evolution des technologies mémoires et perspectives 24 1.2.2 Les erreurs multiples dans les mémoires, p.25
URL : https://hal.archives-ouvertes.fr/in2p3-00020670

.. La-protection-des-fonctions-logiques, 30 1.4.1 Propagation d'une erreur dans une fonction logique, p.33

.. Gestion-des-erreurs-d-'adressage, Une mémoire comme premier composant d'un pipeline, p.100

N. D. Avirneni, V. Subramanian, and A. K. Somani, Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems, 2009 IEEE/IFIP International Conference on Dependable Systems & Networks, pp.185-194, 2009.
DOI : 10.1109/DSN.2009.5270340

R. C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEE Transactions on Device and Materials Reliability, vol.5, issue.3, pp.305-316, 2005.
DOI : 10.1109/TDMR.2005.853449

M. P. Baze and S. P. Buchner, Attenuation of single event induced pulses in CMOS combinational logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2217-2223, 1997.
DOI : 10.1109/23.659038

S. Buchner, M. Baze, D. Brown, D. Mcmorrow, and J. Melinger, Comparison of error rates in combinational and sequential logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2209-2216, 1997.
DOI : 10.1109/23.659037

R. Naseer, S. Dasgupta, A. F. Witulski, J. Sondeen, S. D. Stansberry et al., Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs, Nuclear Science IEEE Transactions on, vol.54, issue.4, pp.935-945, 2007.

D. R. Blum and J. G. Delgado-frias, Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories Circuits and Systems, IEEE International Symposium on, pp.2786-2789, 2007.

J. L. Barth, C. S. Dyer, and E. G. Stassinopoulos, Space, atmospheric, and terrestrial radiation environments, IEEE Transactions on Nuclear Science, vol.50, issue.3, pp.466-482, 2003.
DOI : 10.1109/TNS.2003.813131

J. Benedetto, P. Eaton, K. Avery, D. Mavis, M. Gadlage et al., Heavy ion-induced digital single-event transients in deep submicron Processes, IEEE Transactions on Nuclear Science, vol.51, issue.6, pp.3480-3485, 2004.
DOI : 10.1109/TNS.2004.839173

R. Baumann, T. Hossain, S. Murata, and H. Kitagawa, Boron compounds as a dominant source of alpha particles in semiconductor devices, Reliability Physics Symposium, 1995. 33rd Annual Proceedings., IEEE International, pp.297-302, 1995.

D. Blaauw, S. Kalaiselvan, K. Lai, . Wei-hsiang, . Ma et al., Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance Solid-State Circuits Conference, Digest of Technical Papers. IEEE International, pp.400-622, 2008.

P. D. Bradley and E. Normand, Single event upsets in implantable cardioverter defibrillators, IEEE Transactions on Nuclear Science, vol.45, issue.6, pp.2929-2940, 1998.
DOI : 10.1109/23.736549

R. Perez, M. Nicolaidis, R. Gaillard, M. Derbey, and F. Benistant, Circuit Simulations of SEU and SET Disruptions by Means of an Empirical Model Built Thanks to a Set of 3D Mixed-Mode Device Simulation Responses, Proceedings of RADECS, 2006.

D. Binder, E. C. Smith, and A. B. Holman, Satellite Anomalies from Galactic Cosmic Rays, IEEE Transactions on Nuclear Science, vol.22, issue.6, pp.2675-2680, 1975.
DOI : 10.1109/TNS.1975.4328188

K. A. Bowman, J. W. Tschanz, . Kim, J. C. Lee, C. B. Wilkerson et al., Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance Solid-State Circuits, IEEE Journal, vol.44, issue.1, pp.49-63, 2009.

C. Chen, Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review, IBM Journal of Research and Development, vol.2810, issue.16, pp.124-134, 1984.

G. Université-de, Cisco 12000 Single Event Upset Failures Overview and Work Around Summary, April15, 2003.

M. R. Choudhury and K. Mohanram, Approximate logic circuits for low overhead, non-intrusive concurrent error detection, DATE '08, pp.903-908, 2008.
DOI : 10.1109/date.2008.4484789

A. B. Campbell, O. Musseau, V. Ferlet-cavrois, W. J. Stapor, and . Mcdonald, Analysis of single event effects at grazing angle, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294), pp.1603-1611, 1998.
DOI : 10.1109/RADECS.1997.698992

L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer et al., An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches Solid-State Circuits, IEEE Journal, vol.43, issue.4, pp.956-963, 2008.

T. Calin, M. Nicolaidis, and R. Velazco, Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2874-2878, 1996.
DOI : 10.1109/23.556880

URL : https://hal.archives-ouvertes.fr/hal-00008251

J. Chang, S. Rusu, J. Shoemaker, S. Tam, M. Huang et al., A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor Solid-State Circuits, IEEE Journal, vol.40, issue.1, pp.195-203, 2005.

T. Calin, F. L. Vargas, and M. Nicolaidis, Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments, Proceedings of 1995 IEEE International Test Conference (ITC), pp.45-53, 1995.
DOI : 10.1109/TEST.1995.529816

URL : https://hal.archives-ouvertes.fr/hal-00013893

R. O. Duarte, M. Nicolaidis, H. Bederr, and Y. Zorian, Efficient fault-secure shifter design, Journal of Electronic Testing, vol.12, issue.1/2, pp.29-39, 1998.
DOI : 10.1023/A:1008253000676

URL : https://hal.archives-ouvertes.fr/hal-01413127

E. Dupont, M. Nicolaidis, and P. Rohr, Embedded robustness IPs for transient-error-free ICs, IEEE Design & Test of Computers, vol.19, issue.3, pp.54-68, 2002.
DOI : 10.1109/MDT.2002.1003798

URL : https://hal.archives-ouvertes.fr/hal-00013743

A. Dutta and N. A. Touba, Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code, 25th IEEE VLSI Test Symmposium (VTS'07), pp.349-354, 2007.
DOI : 10.1109/VTS.2007.40

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

A. Dixit and A. Wood, The impact of new technology on soft error rates, 2011 International Reliability Physics Symposium, pp.10-14, 2011.
DOI : 10.1109/IRPS.2011.5784522

T. Austin, K. Flautner, and T. Mudge, Razor, Proceedings of the 19th annual symposium on Integrated circuits and systems design , SBCCI '06, pp.7-18, 2003.
DOI : 10.1145/1150343.1150348

M. Fazeli, A. Namazi, and S. G. Miremadi, An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors, 2009 IEEE/IFIP International Conference on Dependable Systems & Networks, pp.195-204, 2009.
DOI : 10.1109/DSN.2009.5270337

S. Ghosh, S. Basu, and N. A. Touba, Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits, Journal of Low Power Electronics, vol.1, issue.1, pp.63-72, 2005.
DOI : 10.1166/jolpe.2005.007

M. S. Gordon, P. Goldhagen, K. P. Rodbell, T. H. Zabel, H. H. Tang et al., Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground, IEEE Transactions on Nuclear Science, vol.51, issue.6, pp.3427-3434, 2004.
DOI : 10.1109/TNS.2004.839134

R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, A design approach for radiation-hard digital electronics, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.773-778, 2006.
DOI : 10.1145/1146909.1147105

C. Papachristou, Radiation induced single-word multiple-bit upsets correction in SRAM, Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International, pp.266-271, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00013715

G. Université-de, F. Wolff, C. Papachristou, and S. Garverick, An efficient BICS design for SEUs detection and correction in semiconductor memories, Europe, 2005. Proceedings, pp.592-597, 2005.

O. 'gorman and T. J. , The effect of cosmic rays on the soft error rate of a DRAM at ground level, IEEE Transactions on Electron Devices, vol.41, issue.4, pp.553-557, 1994.
DOI : 10.1109/16.278509

O. N. Garcia and T. R. Rao, On the Methods of Checking Logical Operations, Proc. 2nd Annual Princeton Conference on Information Sciences and Systems, pp.89-95, 1968.

K. Gray, Adding error-correcting circuitry to ASIC memory, IEEE Spectrum, vol.37, issue.4, pp.55-60, 2000.
DOI : 10.1109/6.833029

E. L. Hill, M. H. Lipasti, and K. K. Saluja, An accurate flip-flop selection technique for reducing logic SER, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN), pp.128-136, 2008.
DOI : 10.1109/DSN.2008.4630081

E. Ibe, Terrestrial Neutron-Induced Soft Errors In Advanced Memory Devices, 2008.

E. Ibe, S. S. Chung, S. J. Wen, ;. H. Yamaguchi, Y. Yahagi et al., Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling, IEEE Custom Integrated Circuits Conference 2006, pp.437-444, 2006.
DOI : 10.1109/CICC.2006.321010

E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, Scaling Effects on Neutron-Induced Soft Error in SRAMs Down to 22nm Process, Third Workshop on Dependable and Secure Nanocomputing, 2009.

E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule, IEEE Transactions on Electron Devices, vol.57, issue.7, pp.1527-1538, 2010.
DOI : 10.1109/TED.2010.2047907

[. Jedec, Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices: JESD89A, JEDEC STANDARD JEDEC Solid State Technology Association, issue.89, pp.1-85, 2006.

H. Nakamura, T. Yamada, and K. Kumagai, Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation, Electron Devices Meeting IEDM Technical Digest. IEEE International, pp.945-948, 2004.

C. A. Lisboa, F. L. Kastensmidt, E. H. Neto, G. Wirth, and L. Carro, Using built-in sensors to cope with long duration transient faults in future technologies, 2007 IEEE International Test Conference, pp.1-10, 2007.
DOI : 10.1109/TEST.2007.4437631

G. G. Langdon and C. K. Tang, Concurrent Error Detection for Group Look-ahead Binary Adders, IBM Journal of Research and Development, vol.14, issue.5, pp.563-573, 1970.
DOI : 10.1147/rd.145.0563

J. Lo, S. Thanawastien, T. R. Rao, and M. Nicolaidis, An SFS Berger check prediction ALU and its application to self-checking processor designs Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.11, issue.4, pp.525-540, 1992.

S. Lin, . Yong-bin, . Kim, and F. Lombardi, A novel design technique for soft error hardening of Nanoscale CMOS memory, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, pp.679-682, 2009.
DOI : 10.1109/MWSCAS.2009.5236005

R. Mariani and G. Boschi, A system-level approach for embedded memory robustness, Solid-State Electronics, vol.49, issue.11, 2005.
DOI : 10.1016/j.sse.2005.10.008

J. Université-de-grenoble-javaudin, Advanced OFDM Modulators considered in the IST-WINNER Framework for Future Wireless Systems, 14 th IST Mobile and Wireless Communications Submit, 2005.

C. Metra, Trading Off Dependability and Cost for Nanoscale High Performance Microprocessors: The Clock Distribution Problem, Workshop on Dependable and Secure Nanocomputing, 2009.

J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, Characterization of multi-bit soft error events in advanced SRAMs, IEEE International Electron Devices Meeting 2003, pp.8-10, 2003.
DOI : 10.1109/IEDM.2003.1269335

O. Musseau, F. Gardic, P. Roche, T. Corbiere, R. A. Reed et al., Analysis of multiple bit upsets (MBU) in CMOS SRAM, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2879-2888, 1996.
DOI : 10.1109/23.556881

A. Makihara, H. Shindou, N. Nemoto, S. Kuboyama, S. Matsuda et al., Analysis of single-ion multiple-bit upset in high-density DRAMs, IEEE Transactions on Nuclear Science, vol.47, issue.6, pp.2400-2404, 2000.
DOI : 10.1109/23.903783

P. J. Meaney, S. B. Swaney, P. N. Sanda, and L. Spainhower, IBM z990 soft error detection and recovery, IEEE Transactions on Device and Materials Reliability, vol.5, issue.3, pp.419-427, 2005.
DOI : 10.1109/TDMR.2005.859577

B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, M. J. Gadlage, O. A. Amusan et al., Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies, Nuclear Science IEEE Transactions on, vol.54, issue.6, pp.2506-2511, 2007.

M. Nicolaidis and R. O. Duarte, Fault-secure parity prediction Booth multipliers, IEEE Design & Test of Computers, vol.16, issue.3, pp.90-101, 1999.
DOI : 10.1109/54.785842

URL : https://hal.archives-ouvertes.fr/hal-00013808

. Ndm-+-97-]-m, R. O. Nicolaidis, S. Duarte, J. Manich, and . Figueras, Achieving fault secureness in parity prediction arithmetic operators, IEEE Des. Test. Comput, vol.14, issue.3, pp.60-71, 1997.

E. Normand, Single event upset at ground level, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2742-2750, 1996.
DOI : 10.1109/23.556861

J. Olsen, P. E. Becher, P. B. Fynbo, P. Raaby, and J. Schultz, Neutron-induced single event upsets in static RAMS observed a 10 km flight attitude, IEEE Transactions on Nuclear Science, vol.40, issue.2, pp.74-77, 1993.
DOI : 10.1109/23.212319

E. S. Sogomonyan and D. Marienfeld, A modulo p checked selfchecking carry select adder, On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE, pp.25-29, 2003.

D. Université-de-grenoble-marienfeld, E. S. Sogomonyan, and M. Gossel, Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits," On-Line Testing Symposium, IOLTS 2004. Proceedings. 10th IEEE International, pp.31-36, 2004.

W. W. Pet58-]-peterson, On Checking an Adder, IBM Journal of Research and Development, vol.2, issue.2, pp.166-168, 1958.
DOI : 10.1147/rd.22.0166

D. K. Pradhan, Fault-Tolerant Computing System Design, 1996.

R. J. Riedlinger, R. Bhatia, L. Biro, B. Bowhill, E. Fetzer et al., A 32nm 3.1 billion transistor 12-wide-issue Itanium<sup>&#x00AE;</sup> processor for mission-critical servers, 2011 IEEE International Solid-State Circuits Conference, pp.84-86, 2011.
DOI : 10.1109/ISSCC.2011.5746230

D. Radaelli, H. Puchner, . Wong, and S. Daniel, Investigation of multi-bit upsets in a 150 nm technology SRAM device, IEEE Transactions on Nuclear Science, vol.52, issue.6, pp.2433-2437, 2005.
DOI : 10.1109/TNS.2005.860675

M. S. Violante, M. Nicolescu, B. Velazco, and R. , Coping with SEUs/SETs in microprocessors by means of low-cost solutions: A comparative study, IEEE Trans. Nucl. Sci, vol.49, issue.3, pp.1491-1495, 2002.
URL : https://hal.archives-ouvertes.fr/hal-01388756

C. Sahnine, Architecture de circuit intégré reconfigurable, très haut débit et basse consommation pour le traitement numérique de l'OFDM avancé, 2009.

N. M. Sivamangai, K. Gunavathi, and P. Balakrishnan, A BICS Design to Detect Soft Error in CMOS SRAM, International Journal on Computer Science and Engineering, vol.02, issue.03, pp.734-740, 2010.

F. F. Sellers, M. Hsiao, and L. W. Bearnson, Error Detecting Logic for Digital Computers, 1968.

[. Chen and W. K. Fuchs, Compiler-assisted multiple instruction word retry for VLIW architectures Parallel and Distributed Systems, IEEE Transactions on, vol.12, issue.12, pp.1293-1304, 2001.

J. E. Smith and A. R. Pleszkun, Implementing precise interrupts in pipelined processors, IEEE Transactions on Computers, vol.37, issue.5, pp.562-573, 1988.
DOI : 10.1109/12.4607

D. P. Siewiorek and R. S. Swwarz, Reliable Computer Design and Evaluation, 1992.

N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia et al., Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices, 2006 IEEE International Reliability Physics Symposium Proceedings, pp.217-225, 2006.
DOI : 10.1109/RELPHY.2006.251220

S. Baeg-;-shijie-wen and R. Wong, SRAM Interleaving Distance Selection With a Soft Error Failure Model, IEEE Transactions on Nuclear Science, vol.56, issue.4, pp.2111-2118, 2009.
DOI : 10.1109/TNS.2009.2015312

M. E. Sinangil, N. Verma, and A. P. Chandrakasan, A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS Solid-State Circuits, IEEE Journal, vol.44, issue.11, pp.3163-3173, 2009.

S. Lin, . Yong-bin, . Kim, and F. Lombardi, Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset, 2011 IEEE 29th International Conference on Computer Design (ICCD), pp.320-325, 2011.
DOI : 10.1109/ICCD.2011.6081418

H. Université-de-grenoble-ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka et al., Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology, Electron Devices Meeting, pp.941-944, 2004.

N. A. Touba and E. J. Mccluskey, Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection, IEEE/ACM International Conference on Computer-Aided Design, pp.651-654, 1994.
DOI : 10.1109/ICCAD.1994.629891

K. Tanaka, H. Nakamura, T. Uemura, K. Takeuchi, T. Fukuda et al., Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits, 2009 International Conference on Simulation of Semiconductor Processes and Devices, pp.1-4, 2009.
DOI : 10.1109/SISPAD.2009.5290214

Y. Tamir, M. Tremblay, and D. A. Rennels, The implementation and application of micro rollback in fault-tolerant VLSI systems, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, pp.234-239, 1988.
DOI : 10.1109/FTCS.1988.5325

R. Vemu, A. Jas, J. A. Abraham, S. Patil, and R. Galivanche, A low-cost concurrent error detection technique for processor control logic, DATE '08, pp.897-902, 2008.

A. Wood, R. Jardine, and W. Bartlett, Data integrity in HP nonstop servers, Proc. SELSE II, pp.11-12, 2006.

J. T. Wallmark and S. M. Marcus, Minimum Size and Maximum Packing Density of Nonredundant Semiconductor Devices, Proceedings of the IRE, pp.286-298, 1962.
DOI : 10.1109/JRPROC.1962.288321

Y. Liu-;-kaijie and . Wu, Runtime adaptable concurrent error detection for linear digital systems, IEEE 29th International Conference on, pp.261-266, 2011.

J. F. Ziegler and W. A. Lanford, Effect of Cosmic Rays on Computer Memories, Science, vol.206, issue.4420, p.776, 1979.
DOI : 10.1126/science.206.4420.776

S. Mitra, T. M. Mak, N. Seifert, N. J. Wang, Q. Shi et al., Sequential Element Design With Built-In Soft Error Resilience, Very Large Scale Integration (VLSI) Systems, pp.1368-1378, 2006.

@. Nicolaidis, M. Bonnoit, T. Zergainoh, and N. , Eliminating speed penalty in ECC protected memories, 2011 Design, Automation & Test in Europe, pp.1-6, 2011.
DOI : 10.1109/DATE.2011.5763256

URL : https://hal.archives-ouvertes.fr/hal-00671366

@. Bonnoit, T. Nicolaidis, M. Zergainoh, and N. , Towards a tool for implementing delay-free ECC in embedded memories, 2011 IEEE 29th International Conference on Computer Design (ICCD), pp.441-442, 2011.
DOI : 10.1109/ICCD.2011.6081440

URL : https://hal.archives-ouvertes.fr/hal-00671337

@. Bonnoit, T. Nicolaidis, M. Zergainoh, and N. , Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study, Journal of Electronic Testing, vol.37, issue.5
DOI : 10.1007/s10836-013-5386-8

URL : https://hal.archives-ouvertes.fr/hal-01137865