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Architectures pour des circuits fiables de hautes performances

Abstract : Nanometric technologies led to a decrease of electronic circuit reliability, especially against external phenomena. Those may change the state of storage components, or interfere with logical components. In fact, this issue is more critical for memories, as they are more sensitive to external radiations. The error correcting codes are one of the most used solutions. However, reliability constraints require codes that are more and more complex. These codes have a negative effect on the system bandwidth. We propose a generic methodology that removes the timing penalty of error correcting codes during memory's write operation. Moreover, it limits the speed penalty for read operation only in the rare case an error is detected. To proceed, the circuit is decontaminated after uncorrected data were propagated inside the circuit. This technique may require restoring some past states of few storage components by adding some FIFO. An algorithm that identifies these components was also created. Then we try to evaluate the impact of such a technique for the following issue: the global state restoration of a circuit to erase all kinds of soft errors, everywhere inside the circuit.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, June 25, 2013 - 3:51:07 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, September 26, 2013 - 4:20:17 AM


  • HAL Id : tel-00838425, version 1


T. Bonnoit. Architectures pour des circuits fiables de hautes performances. Micro et nanotechnologies/Microélectronique. Université de Grenoble, 2012. Français. ⟨tel-00838425v1⟩



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