Skip to Main content Skip to Navigation
Theses

An electronic system level modeling approach for the design and verification of low-power systems-on chip

Abstract : A SoC power management solution can be defined by a low-power architecture composed of multiple power domains and a power management strategy for power domains states control. If these two elements are energy-efficient, an energy-efficient solution can be obtained. This approach requires inferring power structural elements and their related behavior in the chip internal logic. A strategy adjusting the power domains states must respect structural and functional dependencies due to the physical power domains composition. This strong relationship between power architecture and its management strategy must be explored at early design stages to find the most energy-efficient solution. Low-power design standards have recently enabled low-power architecture exploration starting from the Register Transfer Level (RTL) by defining semantics to specify power architecture, simulate and check its behavior along with the initial functional one. But, these standards miss semantics for reusable power domain control interface making power management strategies exploration tedious. The RTL-based semantics defined by these standards constrain also their use at Transaction-Level of Modeling (TLM) for fast and easy exploration. This dissertation proposes extensions to low-power standards to fill these gaps. It provides a complete study of power optimization opportunities based on composition and management of power domains in Transaction-Level (TL) functional models within a common USLPAF framework. USLPAF includes a methodology that combines design and verification of TL low-power models. To apply this methodology, USLPAF incorporates a library of modeling techniques and built-in features.
Complete list of metadatas

Cited literature [133 references]  Display  Hide  Download

https://tel.archives-ouvertes.fr/tel-00837662
Contributor : Abes Star :  Contact
Submitted on : Monday, November 18, 2013 - 3:42:10 PM
Last modification on : Monday, October 12, 2020 - 10:30:51 AM
Long-term archiving on: : Saturday, April 8, 2017 - 12:55:28 AM

File

2013NICE4023.pdf
Version validated by the jury (STAR)

Identifiers

  • HAL Id : tel-00837662, version 2

Collections

Citation

Ons Mbarek. An electronic system level modeling approach for the design and verification of low-power systems-on chip. Other [cs.OH]. Université Nice Sophia Antipolis, 2013. English. ⟨NNT : 2013NICE4023⟩. ⟨tel-00837662v2⟩

Share

Metrics

Record views

539

Files downloads

1736