R. E. Best, Phase-locked Loops : Design, Simulation, and Applications, 2003.

T. J. Yamaguchi, M. Soma, J. P. Nissen, D. E. Halter, R. Raina et al., Skew Measurements in Clock Distribution Circuits Using an Analytic Signal Method, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23, issue.7, pp.997-1009, 2004.
DOI : 10.1109/TCAD.2004.829814

P. Klein, An Analytical Thermal Noise Model of Deep Submicron MOSFET's, IEEE Electron Device Letters, pp.399-401, 1999.

N. H. Hamid, A. F. Murray, and S. Roy, Time-Domain Modeling of Low-Frequency Noise in Deep-Submicrometer MOSFET, IEEE Transctions on Circuits And Systems-I : Regular Papers, pp.245-257, 2008.

T. H. Chang, Minimizing switching noise in a power distribution network using external coupled resistive termination, IEEE Transactions on Advanced Packaging, vol.28, issue.4, pp.754-760, 2005.
DOI : 10.1109/TADVP.2005.849568

M. Saint-laurent and M. Swaminathan, A multi-PLL clock distribution architecture for gigascale integration, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, pp.30-35, 2001.
DOI : 10.1109/IWV.2001.923136

S. A. Tawfik and V. Kursun, Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, issue.3, pp.347-355, 2010.
DOI : 10.1109/TVLSI.2008.2010549

R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser, Clock skew verification in the presence of IR-drop in the power distribution network, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.6, pp.635-644, 2000.
DOI : 10.1109/43.848085

D. Kasprowicz, Empirical model of skew in clock-distribution grids, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., pp.463-468, 2006.
DOI : 10.1109/MIXDES.2006.1706623

D. W. Bailey and B. J. Benschneider, Clocking design and analysis for a 600-MHz Alpha microprocessor, IEEE Journal of Solid-State Circuits, vol.33, issue.11, pp.1627-1633, 1998.
DOI : 10.1109/4.726547

G. Geannopoulos and X. Dai, An adaptive digital deskewing circuit for clock distribution networks, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156), pp.400-401, 1998.
DOI : 10.1109/ISSCC.1998.672552

J. Stinson and S. Rusu, A 1.5 GHz third generation Itanium R processor, IEEE International Solid-State Circuits Conference, pp.252-492, 2003.

N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor, IEEE Journal of Solid-State Circuits, vol.36, issue.11, pp.1647-1653, 2001.
DOI : 10.1109/4.962284

S. Tam, S. Rusu, U. N. Desai, R. Kim, and J. , Clock generation and distribution for the first IA-64 microprocessor, IEEE Journal of Solid-State Circuits, vol.35, issue.11, pp.1545-1552, 2000.
DOI : 10.1109/4.881198

H. Mizuno and K. Ishibashi, A Noise-Immune GHz-Clock Distribution Scheme using Synchronous Distributed Oscillators, IEEE International Solid-State Circuits Conference, pp.404-405, 1998.

G. A. Pratt and J. Nguyen, Distributed synchronous clocking, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.3, pp.314-328, 1995.
DOI : 10.1109/71.372779

V. Gutnik and A. P. Chandrakasan, Active GHz clock network using distributed PLLs, IEEE Journal of Solid-State Circuits, vol.35, issue.11, pp.1553-1560, 2000.
DOI : 10.1109/4.881199

H. J. Choi and W. C. Lindsey, Phase and Frequency Transfer Analysis of N Mutually Synchronized Oscillators, IEEE Transactions on Aerospace and Electronic Systems, vol.20, issue.6, pp.748-753, 1984.
DOI : 10.1109/TAES.1984.310458

J. Chen and W. C. Lindsey, Mutual Clock Synchronization in Global Digital Communication Networks, IEEE Vehicular Technology Conference, vol.2, pp.1244-1248, 1996.

G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas et al., Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor, IEEE Micro, vol.23, issue.6, pp.62-68, 2003.
DOI : 10.1109/MM.2003.1261388

M. Dongsheng and R. Bondade, Enabling Power-Efficient DVFS Operations on Silicon, IEEE Circuits and Systems Magazine, pp.14-30, 2010.

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, pp.42-51, 2008.
DOI : 10.1109/JSSC.2007.910966

J. M. Scorletti, J. Akre, and . Juillard, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE International Symposium on Circuits and Systems, pp.2589-2592, 2011.

J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors, IEEE Journal of Solid-State Circuits, vol.30, issue.4, pp.412-422, 1995.
DOI : 10.1109/4.375961

T. Olsson, P. Nilsson, T. Meincke, A. Hemani, and M. Torkelson, A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), pp.13-16, 2000.
DOI : 10.1109/ISCAS.2000.855983

T. Olsson and P. Nilsson, A digitally controlled PLL for SoC applications, IEEE Journal of Solid-State Circuits, vol.39, issue.5, pp.751-760, 2004.
DOI : 10.1109/JSSC.2004.826333

H. Song, D. Kim, D. Oh, S. Kim, and D. Jeong, A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control, IEEE Journal of Solid-State Circuits, vol.46, issue.2, pp.424-434, 2011.
DOI : 10.1109/JSSC.2010.2082272

URL : https://hal.archives-ouvertes.fr/in2p3-00004486

T. Olsson and P. Nilsson, Fully integrated standard cell digital PLL, Electronics Letters, vol.37, issue.4, pp.211-212, 2001.
DOI : 10.1049/el:20010160

R. K. Pokharel, A. Tomar, H. Kanaya, and K. Yoshida, Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process, 2008 China-Japan Joint Microwave Conference, pp.623-626, 2008.
DOI : 10.1109/CJMW.2008.4772508

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, pp.42-51, 2008.
DOI : 10.1109/JSSC.2007.910966

. Friedman, A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24- to-32GHz Operation in 65nm CMOS, IEEE Solid State Circuits Conference, pp.516-632, 2008.

E. Zianbetov, F. Anceau, M. Javidan, D. Galayko, E. Colinet et al., A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.2845-2848, 2011.
DOI : 10.1109/ISCAS.2011.5938198

URL : https://hal.archives-ouvertes.fr/hal-00683074

P. Chen, C. Chung, and C. Lee, A Portable Digitally Controlled Oscillator Using Novel Varactors, IEEE Transctions on Circuits And Systems-II : Express Briefs, pp.233-237, 2005.

A. S. Kamath, B. Chattopadhyay, and G. Nayak, A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0, 2009 IEEE Custom Integrated Circuits Conference, pp.547-550, 2009.
DOI : 10.1109/CICC.2009.5280765

A. A. Abidi, Phase Noise and Jitter in CMOS Ring Oscillators, IEEE Journal of Solid-State Circuits, vol.41, issue.8, pp.1803-1816, 2006.
DOI : 10.1109/JSSC.2006.876206

M. Alioto and G. Palumbo, Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison, IEEE Transactions on Very Large Scale Integration Systems, pp.1322-1335, 2006.
DOI : 10.1109/TVLSI.2006.887809

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, pp.42-51, 2008.
DOI : 10.1109/JSSC.2007.910966

D. A. Badillo and S. Kiaei, A low phase noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), pp.533-536, 2004.
DOI : 10.1109/ISCAS.2004.1329058

G. Sarivisetti, E. Kougianos, P. S. Saraju, A. Palakodety, and A. K. , Optimization of a 45nm CMOS voltage controlled oscillator using design of experiments, 2006 IEEE Region 5 Conference, pp.87-90, 2006.
DOI : 10.1109/TPSD.2006.5507456

A. Hajimiri and T. H. Lee, Design of Low Noise Oscillators, Kluwer Academic, 1999.

K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, A physics-based MOSFET noise model for circuit simulators, IEEE Transactions on Electron Devices, vol.37, issue.5, pp.1323-1333, 1990.
DOI : 10.1109/16.108195

C. Liu, Jitter in Oscillators with 1/f Noise Sources and Application to True RNG for Cryptography, Thèse de doctorat, 2006.

T. Olsson and P. Nilsson, A digitally controlled PLL for SoC applications, IEEE Journal of Solid-State Circuits, vol.39, issue.5, pp.751-760, 2004.
DOI : 10.1109/JSSC.2004.826333

T. Sakurai and A. R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid-State Circuits, vol.25, issue.2, pp.584-594, 1990.
DOI : 10.1109/4.52187

E. Morifuji, T. Yoshida, H. Tsuno, Y. Kikuchi, S. Matsuda et al., New guideline of Vdd and Vth scaling for 65nm technology and beyond, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., pp.164-165, 2004.
DOI : 10.1109/VLSIT.2004.1345457

S. Docking and M. Sachdev, A Method to Derive an Equation for the Oscillation Frequency of a Ring Oscillator, IEEE Transaction on Circuits And Systems -I, pp.259-264, 2003.

M. Alioto and G. Palumbo, Oscillation Frequency in CML and ESCL Ring Oscillators, IEEE Transaction on Circuits And Systems -I, pp.210-214, 2001.

]. E. Bibliographie1, F. Zianbetov, M. Anceau, D. Javidan, E. Galayko et al., A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation, IEEE International Symposium on Circuits And Systems, pp.2845-2848, 2011.

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, pp.42-51, 2008.
DOI : 10.1109/JSSC.2007.910966

X. Zhang, A. B. Apsel, and . Low-power, Process-and-Temperature-Compensated Ring Oscillator With Addition-Based Current Source, IEEE Transctions on Circuits And Systems-I : Regular Papers, pp.868-878, 2011.

K. N. Leung, C. H. Lo, P. K. Mok, Y. Y. Mai, W. Y. Leung et al., Temperaturecompensated CMOS ring oscillator for power-management circuits, IEEE Electronics Letters, vol.43, pp.15-786, 2007.

P. Heydari, Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise, IEEE Transctions on Circuits And Systems-I : Regular Papers, pp.2404-2416, 2004.

A. Hajimiri and T. H. Lee, Design of Low Noise Oscillators, Kluwer Academic, 1999.

W. Xu, X. Chen, and J. Wu, An overview of theory and techniques for reducing ring oscillator supply voltage sensitivity in mixed-signal SoC, 2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC), pp.2039-2042, 2011.
DOI : 10.1109/MEC.2011.6025891

P. Hsieh, J. Maxey, and C. Yang, Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages, IEEE Journal of Solid-State Circuits, vol.44, issue.9, pp.2488-2495, 2009.
DOI : 10.1109/JSSC.2009.2025406

Q. Sun, Y. Zhang, C. Hu-guo, K. Jaaskelainen, and Y. Hu, A Supply-Noise-Insensitive PLL in Monolithic Active Pixel Sensors, IEEE Sensors Journal, vol.11, issue.10, pp.2212-2219, 2011.
DOI : 10.1109/JSEN.2011.2104946

B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine, Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 2007.
DOI : 10.1109/DATE.2007.364426

URL : https://hal.archives-ouvertes.fr/lirmm-00178525

J. C. Ku and Y. Ismail, On the Scaling of Temperature-Dependent Effects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.10, pp.1882-1888, 2007.
DOI : 10.1109/TCAD.2007.895774

I. Hwang, S. Song, and S. Kim, A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition, IEEE Journal of Solid-State Circuits, vol.36, issue.10, pp.1574-1581, 2001.
DOI : 10.1109/4.953487

F. Herzel and B. Razavi, A Study of Oscillator Jitter Due to Supply and Substrate Noise, IEEE Transctions on Circuits And Systems-II : Analog and Digital Signal Processing, pp.56-62, 1999.

N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor, IEEE Journal of Solid-State Circuits, vol.36, issue.11, pp.1647-1653, 2001.
DOI : 10.1109/4.962284

P. Heydari, Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise, IEEE Transctions on Circuits And Systems-I : Regular Papers, pp.2404-2416, 2004.

T. Ueno, T. Yamaji, and T. Itakura, A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.90, issue.2, pp.365-371, 2007.
DOI : 10.1093/ietfec/e90-a.2.365

URL : https://hal.archives-ouvertes.fr/inserm-00673126

M. Albiol, J. L. González, and E. Alarcón, Improved design methodology for high-speed high-accuracy current steering D/A converters, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.636-641, 2003.
DOI : 10.1109/DATE.2003.1253679

S. Docking and M. Sachdev, A Method to Derive an Equation for the Oscillation Frequency of a Ring Oscillator, IEEE Transactions on Circuits And Systems -I : Fundamental Theory and Applications, pp.259-264, 2003.

F. Maloberti, Analog Design for CMOS VLSI Systems, 2001.

P. Mandal and V. Visvanathan, A self-biased high performance folded cascode CMOS op-amp, Proceedings Tenth International Conference on VLSI Design, pp.429-434, 1997.
DOI : 10.1109/ICVD.1997.568171

J. C. Ku and Y. Ismail, On the Scaling of Temperature-Dependent Effects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.10, pp.1882-1888, 2007.
DOI : 10.1109/TCAD.2007.895774

X. Zhang, A. B. Apsel, and . Low-power, Process-and-Temperature-Compensated Ring Oscillator With Addition-Based Current Source, IEEE Transctions on Circuits And Systems-I : Regular Papers, pp.868-878, 2011.

K. Sundaresan, P. E. Allen, and F. Ayazi, Process and Temperature Compensation in a 7-MHz CMOS Clock Oscillator, IEEE Journal of Solid-State Circuits, vol.41, issue.2, pp.433-442, 2006.
DOI : 10.1109/JSSC.2005.863149

I. M. Filanovsky and A. Allam, Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits, IEEE Transactions on Circuits And Systems -I : Fundamental Theory and Applications, pp.876-884, 2001.

Y. Taur, MOSFET channel length: extraction and interpretation, IEEE Transactions on Electron Devices, vol.47, issue.1, pp.160-170, 2000.
DOI : 10.1109/16.817582

. Stmicroelectronics, CMOS065 technology HPA LP MOS transistor models -Release V1.0a, Models for DK5

B. Razavi, A study of phase noise in CMOS oscillators, IEEE Journal of Solid-State Circuits, vol.31, issue.3, pp.331-343, 1996.
DOI : 10.1109/4.494195

B. Moon, Y. Park, and D. Jeong, Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.55, issue.10, pp.1036-1040, 2008.
DOI : 10.1109/TCSII.2008.926793

S. Seo, J. Chun, Y. Jun, S. Kim, and K. Kwon, A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.58, issue.10, pp.632-636, 2011.
DOI : 10.1109/TCSII.2011.2164146

A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, A 0.4-to-3 GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Backgournd Calibration, IEEE Solid State Circuits Conference, pp.438-450, 2011.

R. Kumar and V. Kursun, Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies, 2006 IEEE International Symposium on Circuits and Systems, pp.3858-3861, 2006.
DOI : 10.1109/ISCAS.2006.1693470