Model-based design for on-chip systems using and extending Marte and IP-XACT

Aamir Mehmood Khan 1
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : On-chip systems (also known as System-on-chip or SoC) are more and more complex. SoC design heavily relies on reuse of building blocks, called IPs (Intellectual Property). These IPs are built by different designers working with different tools. So, there is an urgent demand for interoperability of IPs, that is, ensuring format compatibility and unique interpretation of the descriptions. IP-Xact is a de facto standard de fined in the context of electronic system design to provide portable representations of (electronic) components and IPs. It succeeds in syntactic compatibility but neglects the behavioral aspects. UML is a classical modeling language for software engineering. It provides several model elements to cover all aspects of a design (structural and behavioral). We advocate a joint use of UML and IP-Xact to achieve the required interoperability. More specifically, we reuse the UML Pro file for MARTE to extend UML elements with specific features for embedded and real-time systems. MARTE Generic Resource Modeling (GRM) package is extended to add IP-Xact structural features. MARTE Time Model extends the untimed UML with an abstract concept of time, adequate to model at the Electronic System Level. The first contribution of this thesis is the definition of an IP-xact domain model. This domain model is used to build a UML Profile for IP-Xact that reuses, as much as possible, MARTE stereotypes and defines new ones only when required. A model transformation has been implemented in ATL to use UML graphical editors as front-ends for the specification of IPs and to generate IP- xact code. The second contribution addresses the modeling of the IP time properties and constraints. UML behavioral diagrams are enriched with logical clocks and clock constraints using the MARTE Clock Constraint Specification Language (CCSL). The CCSL specification can serve as a golden model for the expected time behavior and the verification of candidate implementations at different abstraction levels (RTL or TLM). Time properties are verified through the use of a dedicated library of observers.
keyword : MARTE ESL IP-Xact
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Aamir Mehmood Khan. Model-based design for on-chip systems using and extending Marte and IP-XACT. Embedded Systems. Université Nice Sophia Antipolis, 2010. English. ⟨NNT : 2010NICE4002⟩. ⟨tel-00834283⟩

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