R. Asghar and D. Liu, Towards Radix-4, Parallel Interleaver Design to Support High-Throughput Turbo Decoding for Re-Configurability " 33rd IEEE SARNOFF Symposium, 2010.

J. [. Bahl, F. Cocke, J. L. Jelinek, J. Bahl, F. Cocke et al., Optimal decoding of linear codes for minimizing symbol error rate (Corresp.), IEEE Transactions on Information Theory, vol.20, issue.2, pp.284-287, 1974.
DOI : 10.1109/TIT.1974.1055186

A. Batra, Design of a Multiband OFDM System for Realistic UWB Channel Environments, IEEE Transactions on Microwave Theory and Techniques, vol.52, issue.9, pp.2123-2138, 2004.
DOI : 10.1109/TMTT.2004.834184

M. S. Bazaraa and J. J. Jarvis, Linear Programming and Network Flows, 1997.
DOI : 10.1002/9780471703778

A. [. Berrou, P. Glavieux, and . Thitimajshima, Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1, Proceedings of ICC '93, IEEE International Conference on Communications, pp.1064-1070, 1993.
DOI : 10.1109/ICC.1993.397441

A. J. Blanksby, C. J. Howland-blankenship, B. Classon, and V. Deai, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder, Proc. Int. Conf. 3G Wireless and Beyond, pp.404-412, 2002.
DOI : 10.1109/4.987093

N. G. De-bruijn, A Combinatorial Problem, Koninklijke Nederlandse Akademie v. Wetenschappen, vol.49, pp.758-764, 1946.

C. Chavet and P. Coussy, A memory mapping approach for parallel interleaver design with multiples read and write accesses, Proceedings of 2010 IEEE International Symposium on Circuits and Systems
DOI : 10.1109/ISCAS.2010.5537955

URL : https://hal.archives-ouvertes.fr/hal-00482682

]. C. Cha10a, P. Chavet, P. Coussy, E. Urard, and . Martin, Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architecture, 2010.

J. Chen and M. Fossorier, Density evolution for two improved BP-Based decoding algorithms of LDPC codes, IEEE Communications Letters, vol.6, issue.5, 2002.
DOI : 10.1109/4234.1001666

R. Cole and J. Hopcroft, On Edge Coloring Bipartite Graphs, SIAM Journal on Computing, vol.11, issue.3, pp.540-546, 1982.
DOI : 10.1137/0211043

D. Documenta122, Frame structure channel coding and modulation for the second generation digital terrestrial television broadcasting system (DVB-T2), 2008.

P. [. Fanucci, G. Ciao, and . Colavolpe, VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.89, issue.7, pp.1976-1986, 2006.
DOI : 10.1093/ietfec/e89-a.7.1976

M. [. Fossorier, H. Mihaljevic, and . Imai, Reduced complexity iterative decoding of low-density parity check codes based on belief propagation, IEEE Transactions on Communications, vol.47, issue.5, pp.673-680, 1999.
DOI : 10.1109/26.768759

. [. Gabow, Using euler partitions to edge color bipartite multigraphs, International Journal of Computer & Information Sciences, vol.2, issue.4, pp.345-355, 1976.
DOI : 10.1007/BF00998632

L. [. Giulietti, A. Perre, and . Strum, Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements, Electronics Letters, vol.38, issue.5, pp.232-234, 2002.
DOI : 10.1049/el:20020148

D. Gnaedig, E. Boutillon, M. Jezequel, V. C. Gaudet, and P. G. Gulak, On multiple slice turbo codes, Proc. 3rd Int. Symp. Turbo Codes, Related Topics, pp.343-346, 2003.

M. J. Golay, Complementary series, IEEE Transactions on Information Theory, vol.7, issue.2, pp.82-87, 1961.
DOI : 10.1109/TIT.1961.1057620

J. L. Gross and J. Yellen, Handbook of Graph Theory, 2003.
DOI : 10.1201/9780203490204

R. R. Hamming, The Bell System Technical Journal, Bell Syst. Tech. J, vol.XXVI, issue.2, pp.147-160, 1950.

D. Hartvigsen, Finding maximum square-free 2-matchings in bipartite graphs, Journal of Combinatorial Theory, Series B, vol.96, issue.5, pp.693-705, 2006.
DOI : 10.1016/j.jctb.2006.01.004

S. J. Johnson, Iterative Error Correction Turbo, Low-Density Parity-Check and Repeat?Accumulate Codes, UWB Communications Systems: A Comprehensive Overview " EURASIP Series on Signal Processing and Communications, 2005.

P. Keyngnaert, B. Demoen, B. D. Sutter, B. D. Sus, and K. De-bosschere, Conflict Graph Based Allocation of Static Objects to Memory Banks, Informal proceedings of the First workshop on Semantic, Program Analysis, and Computing Environments, pp.131-142, 2001.

F. Kienle, M. J. Thul, and N. When, Implementation Issues of Scalable LDPC- Decoders, Proceeding of 3 rd International Symposium on Turbo Codes and Related Topics, pp.291-294, 2003.

D. König, Graphok és alkalmazásuk a determinánsok és a halmazok elméletére, Mathematikai és Természettudományi Értzsitö, vol.34, pp.101-119, 1916.

. [. Kozen, The Design and Analysis of Algorithms, 1992.
DOI : 10.1007/978-1-4612-4400-4

J. Kwak and K. Lee, Design of dividable interleaver for parallel decoding in turbo codes, Electronics Letters, vol.38, issue.22, pp.1362-1364, 2002.
DOI : 10.1049/el:20020916

[. Lee and H. Ryu, A 1-Gb/s flexible LDPC decoder supporting multiple code rates and block lengths, IEEE Transactions on Consumer Electronics, vol.54, issue.2, pp.417-424, 2008.
DOI : 10.1109/TCE.2008.4560109

S. Lin, D. J. Costello, and J. , Error control Coding " Pearson Education, 2004.

. Jing-ling, Parallel Interleavers Through Optimized Memory Address Remapping, IEEE Trans. VLSI Systems, vol.18, issue.6, pp.978-987, 2010.

M. Mansour and N. Shanbhag, High-throughput LDPC decoders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.11, issue.6, pp.976-996, 2003.
DOI : 10.1109/TVLSI.2003.817545

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.316.380

F. [. Masera, F. Quaglio, and . Vacca, Implementation of a Flexible LDPC Decoder, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.54, issue.6, pp.542-546, 2007.
DOI : 10.1109/TCSII.2007.894409

H. Moussa, O. Muller, A. Baghdadi, and M. Jezequel, Butterfly and Benes-based onchip communication networks for multiprocessor turbo decoding, Proc. of the conference on Design, Automation and Test in Europe, pp.654-659, 2007.

A. [. Moussa, M. Baghdadi, and . Jezequel, Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder, 2008 IEEE International Symposium on Circuits and Systems, pp.97-100, 2008.
DOI : 10.1109/ISCAS.2008.4541363

H. Moussa, A. Baghdadi, and M. , Binary de Bruijn on-chip netwok for a flexible multiprocessor LDPC decoder " .45 th ACM, IEEE DAC, pp.429-434, 2008.

V. Nagarajan, N. Jayakumar, S. Khatri, and G. Milenkovic, High-throughput VLSI implementations of iterative decoders and related code construction problems, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04., pp.361-365, 2004.
DOI : 10.1109/GLOCOM.2004.1377970

M. [. Neeb, N. Thul, and . Wehn, Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders, 2005 IEEE International Symposium on Circuits and Systems, pp.1766-1769, 2005.
DOI : 10.1109/ISCAS.2005.1464950

[. Pearl, The Four Color Problem Academic Press, Probabilistic Reasoning in Intelligent Systems: Networks of Plausible reference, 1967.

F. Quaglio, F. Vacca, C. Castellano, A. Tarable, and M. G. Asera, Interconnection framework for high-throughput, flexible LDPC decoders, Proceedings of the Design Automation & Test in Europe Conference, 2006.
DOI : 10.1109/DATE.2006.243815

A. Sani, P. Coussy, and C. Chavet, Eric Martin: Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach, ICECS, vol.2010, pp.466-469

A. Sani, P. Coussy, C. Chavet, and E. Martin, An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.1720-1723
DOI : 10.1109/ISCAS.2011.5937914

[. Sani, P. Coussy, C. Chavet, and E. Martin, A methodology based on Transportation problem modeling for designing parallel interleaver architectures, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1613-1616
DOI : 10.1109/ICASSP.2011.5946806

. [. Schrijver, Bipartite Edge Coloring in $O(\Delta m)$ Time, SIAM Journal on Computing, vol.28, issue.3, pp.841-846, 1998.
DOI : 10.1137/S0097539796299266

C. E. Shannon, A mathematical theoryof communication, Bell System Tech, J, vol.27, pp.379-423, 1948.

K. [. Siriwongpairat, . Ray, and . Liu, Ultra-Wideband Communications Systems, 2008.
DOI : 10.1002/9780470179765

J. Sun and O. Y. Takeshita, Interleavers for turbo codes using permutation polynomials over integer rings, IEEE Trans. Inf. Theory, vol.51, issue.1, pp.101-119, 2005.

O. Y. Takeshita, On maximum contention-free interleavers and permutation polynomials over integer rings, IEEE Transactions on Information Theory, vol.52, issue.3, pp.1249-1253, 2006.
DOI : 10.1109/TIT.2005.864450

A. Tarable, S. Benedetto, and G. Montorsi, Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures, IEEE Transactions on Information Theory, vol.50, issue.9, pp.2002-2009, 2004.
DOI : 10.1109/TIT.2004.833353

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.96.5015

A. Tarable and S. Benedetto, Further results on mapping functions, IEEE Information Theory Workshop, 2005., pp.221-225
DOI : 10.1109/ITW.2005.1531893

T. Theocharides, G. Link, N. Vijaykrishnan, and M. J. Irwin, Implementing LDPC decoding on network-on-chip, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp.134-137, 2005.
DOI : 10.1109/ICVD.2005.109

M. Thul, N. Wehn, and L. Rao, Enabling high-speed turbo-decoding through concurrent interleaving, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), pp.897-900, 2002.
DOI : 10.1109/ISCAS.2002.1009986

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.9727

M. I. Thul, F. Gilbert, and N. Wehn, Optimized Concurrent Interleaving for High-speed Turbo-Decoding, Proc. 9rh IEEE International Conference on Electronics, Circuits and Systems -ICECS 2002, 2002.

M. Thul, F. Gilbert, and N. Wehn, Concurrent interleaving architectures for highthroughput channel coding, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.613-616, 2003.

[. P802, 02, Part 11 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Enhancements for Higher Throughput, 2008.

C. Wong and H. Chang, Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, issue.7, pp.566-570, 2010.
DOI : 10.1109/TCSII.2010.2048481

J. P. Woodard and L. Hanzo, Comparative study of turbo decoding techniques: an overview, IEEE Transactions on Vehicular Technology, vol.49, issue.6, pp.2208-2233, 2000.
DOI : 10.1109/25.901892

T. Zhang and K. K. Parhi, Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256), pp.1232-1236, 2001.
DOI : 10.1109/ACSSC.2001.987687

K. [. Zhang and . Parhi, Parallel turbo decoding, Proceedings of the ISCAS '04, pp.23-26, 2004.

L. Zhou, C. Wakayama, and C. R. Shi, CASCADE: a standard super-cell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large scale integrated circuits, IEEE Trans. Computer-Aided Design, issue.7, 2007.

A. Sani, P. Coussy, C. Chavet, and E. Martin, Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach, 2010 17th IEEE International Conference on Electronics, Circuits and Systems, pp.466-469
DOI : 10.1109/ICECS.2010.5724550

URL : https://hal.archives-ouvertes.fr/hal-00551432

A. Sani, P. Coussy, C. Chavet, and E. Martin, An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.1720-1723
DOI : 10.1109/ISCAS.2011.5937914

[. Sani, P. Coussy, C. Chavet, and E. Martin, A methodology based on Transportation problem modeling for designing parallel interleaver architectures, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1613-1616
DOI : 10.1109/ICASSP.2011.5946806

. National, P. Sani, C. Coussy, E. Chavet, and . Martin, A Bipartite Edge Coloring Approach for designing Parallel Interleaver architecture, Colloque National du GDR SoC-SiP, 2010.

A. Sani, P. Coussy, C. Chavet, and E. Martin, Designing Parallel Interleaver architecture through Tripartite Edge Coloring Approach, Colloque National du GDR SoC-SiP, 2011.