A. Eiche, D. Chillet, S. Pillement, and O. Sentieys, Task placement for dynamic and partial reconfigurable region, Proceedings of the Conference on Design and Architectures for Signal and Image Processing, pp.82-88, 2010.

D. Andrews, W. Peck, J. Agron, K. Preston, E. Komp et al., hthreads: A Hardware/Software Co-Designed Multithreaded RTOS Kernel, 2005 IEEE Conference on Emerging Technologies and Factory Automation, 2005.
DOI : 10.1109/ETFA.2005.1612697

D. Aoun, A. Déplanche, and Y. Trinquet, Pfair scheduling improvement to reduce interprocessor migrations, 16th International Conference on Real-Time and Network Systems, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00336513

S. K. Baruah, N. K. Cohen, C. G. Plaxton, and D. A. Varvel, Proportionate progress, Proceedings of the twenty-fifth annual ACM symposium on Theory of computing , STOC '93, pp.345-354, 1993.
DOI : 10.1145/167088.167194

S. K. Baruah, Fairness in periodic real-time scheduling, Proceedings 16th IEEE Real-Time Systems Symposium, pp.200-209, 1995.
DOI : 10.1109/REAL.1995.495210

K. Bazargan, R. Kastner, and M. Sarrafzadeh, Fast template placement for reconfigurable computing systems, IEEE Design & Test of Computers, vol.17, issue.1, pp.68-83, 2000.
DOI : 10.1109/54.825678

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.14.8121

T. Becker, W. Luk, and P. Y. Cheung, Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), pp.35-44, 2007.
DOI : 10.1109/FCCM.2007.51

I. Benkermi, D. Chillet, S. Pillement, and O. Sentieys, Hardware Task Scheduling for Heterogeneous SoC Architectures, European Signal Processing Conference, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00536691

G. Brebner, The swappable logic unit: a paradigm for virtual hardware, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186), pp.77-86, 1997.
DOI : 10.1109/FPGA.1997.624607

C. Cardeira and Z. Mammeri, Handling precedence constraints with neural network based real-time scheduling algorithms, Proceedings Ninth Euromicro Workshop on Real Time Systems, pp.207-214, 1997.
DOI : 10.1109/EMWRTS.1997.613787

C. Cardeira and Z. Mammeri, PREEMPTIVE AND NON-PREEMPTIVE REAL-TIME SCHEDULING BASED ON NEURAL NETWORKS, The 13th IFAC Workshop on Distributed Computer Control Systems, pp.67-72, 1995.
DOI : 10.1016/B978-0-08-042593-1.50015-8

D. Chillet, A. Eiche, S. Al-'bastien-pillement, and O. Sentieys, Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network, Journal of Systems Architecture, vol.57, issue.4, pp.340-353, 2011.
DOI : 10.1016/j.sysarc.2011.01.004

URL : https://hal.archives-ouvertes.fr/hal-00650650

D. Chillet, S. Pillement, and O. Sentieys, RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on??Reconfigurable System-on-Chip, Algorithm-Architecture Matching for Signal and Image Processing, 2010.
DOI : 10.1007/978-90-481-9965-5_6

URL : https://hal.archives-ouvertes.fr/inria-00480545

E. G. Coffman-jr, M. R. Garey, and D. S. Johnson, Approximation Algorithms for Bin-Packing ??? An Updated Survey, Approximation algorithms for NP-hard problems, pp.46-93, 1996.
DOI : 10.1007/978-3-7091-4338-4_3

K. Compton and S. Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys, vol.34, issue.2, pp.171-210, 2002.
DOI : 10.1145/508352.508353

S. Corbetta, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto et al., Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration, IEEE Transactions on Very Large Scale Integration Systems, pp.1650-1654, 2009.
DOI : 10.1109/TVLSI.2008.2005670

J. Cui, Z. Gu, W. Liu, and Q. Deng, An Efficient Algorithm for Online Soft Real-Time Task Placement on Reconfigurable Hardware Devices, 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07), pp.321-328, 2007.
DOI : 10.1109/ISORC.2007.18

K. Danne, Memory management to support multitasking on fpga based systems, Proceedings of the International Conference on Reconfigurable Computing and FPGAs, 2004.

Q. Deng, F. Kong, N. Guan, M. Lv, and W. Yi, On-Line Placement of Real-Time Tasks on 2D Partially Run-Time Reconfigurable FPGAs, 2008 Fifth IEEE International Symposium on Embedded Computing, pp.20-25, 2008.
DOI : 10.1109/SEC.2008.55

M. L. Dertouzos and A. K. Mok, Multiprocessor online scheduling of hard-real-time tasks, IEEE Transactions on Software Engineering, vol.15, issue.12, pp.1497-1506, 1989.
DOI : 10.1109/32.58762

R. P. Dick, D. L. Rhodes, and W. Wolf, TGFF, Proceedings of the sixth international workshop on Hardware/software codesign , CODES/CASHE '98, pp.97-101, 1998.
DOI : 10.1145/278241.278309

A. Eiche, D. Chillet, S. Pillement, O. Sentieys, S. Fekete et al., Parallel Evaluation of Hopfield Neural Networks Optimal FPGA module placement with temporal precedence constraints, NCTA, International Conference on Neural Computation Theory and Applications Proceedings of the IEEE/ACM Design, Automation and Test in Europe conference, pp.658-667, 2001.

F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, and D. Sciuto, Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead, 2006 International Symposium on System-on-Chip, pp.1-4, 2006.
DOI : 10.1109/ISSOC.2006.322008

S. Garcia and B. Granado, OLLAF: A Fine Grained Dynamically Reconfigurable Architecture for OS Support, EURASIP Journal on Embedded Systems, vol.2009, 2009.
DOI : 10.1155/2009/574716

URL : https://hal.archives-ouvertes.fr/hal-00665805

S. Garcia, J. Prévotet, and B. Granado, Hardware task context management for fine grained dynamically reconfigurable architecture, DASIP'07, 2007.

J. Hagemeyer, B. Kettelhoit, M. Koester, and M. Porrmann, Design of homogeneous communication infrastructures for partially reconfigurable fpgas, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), 2007.

M. Handa, Online Placement and Scheduling Algorithms and Methodologies for Reconfigurable Computing Systems, 2004.

M. Handa and R. Vemuri, Area fragmentation in reconfigurable operating systems, Engineering of Reconfigurable Systems and Algorithms, 2004.

R. Hartenstein, M. Herz, and F. Gilbert, Designing for Xilinx XC6200 FPGAs, Programmable Logic and Applications From FPGAs to Computing Paradigm, pp.29-38, 1007.
DOI : 10.1007/BFb0055230

S. Haykin, Neural Networks : A Comprehensive Foundation, 1998.

D. Hebb, The organization of behavior ; a neuropsychological theory, 1949.

J. Hopfield, Neural networks and physical systems with emergent collective computational abilities., Proceedings of the National Academy of Sciences, pp.2554-2558, 1982.
DOI : 10.1073/pnas.79.8.2554

J. Hopfield and D. Tank, Neural " computation of decisions in optimization problems, Biological cybernetics, vol.52, issue.3, pp.141-152, 1985.

E. Horta and J. W. Lockwood, PARBIT : a tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs), Dept. Comput. Sci, 2001.

H. Kalte, G. Lee, M. Porrmann, and U. Ruckert, REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems, 19th IEEE International Parallel and Distributed Processing Symposium, pp.151-151
DOI : 10.1109/IPDPS.2005.380

H. Kalte and M. Porrmann, REPLICA2Pro, Proceedings of the 3rd conference on Computing frontiers , CF '06, pp.403-412, 2006.
DOI : 10.1145/1128022.1128045

H. Kalte, M. Porrmann, and U. Ruckert, System-on-programmable-chip approach enabling online fine-grained 1D-placement, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., p.141, 2004.
DOI : 10.1109/IPDPS.2004.1303118

N. Kamiura, T. Isokawa, and N. Matsui, On Improvement in Fault Tolerance of Hopfield Neural Networks, 13th Asian Test Symposium, pp.406-411, 2004.
DOI : 10.1109/ATS.2004.64

Y. Kamp and M. Hasler, Recursive neural networks for associative memory, 1990.

D. Koch, A. Ahmadinia, C. Bobda, and H. Kalte, FPGA architecture extensions for preemptive multitasking and hardware defragmentation, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921), pp.433-436, 2004.
DOI : 10.1109/FPT.2004.1393318

M. Koester, W. Luk, J. Hagemeyer, M. Porrmann, and U. Ruckert, Design Optimizations for Tiled Partially Reconfigurable Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.6, pp.1-14, 2010.
DOI : 10.1109/TVLSI.2010.2044902

M. Koester, M. Porrmann, and H. Kalte, Task placement for heterogeneous reconfigurable architectures, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005., pp.43-50, 2005.
DOI : 10.1109/FPT.2005.1568523

M. Koester, M. Porrmann, and H. Kalte, Relocation and defragmentation for heterogeneous reconfigurable systems, International Conference on Engineering of Reconfigurable Systems and Algorithms, pp.70-76, 2006.

J. Lehoczky, L. Sha, and Y. Ding, The rate monotonic scheduling algorithm: exact characterization and average case behavior, [1989] Proceedings. Real-Time Systems Symposium, pp.166-171, 1989.
DOI : 10.1109/REAL.1989.63567

C. L. Liu and J. W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM, vol.20, issue.1, pp.46-61, 1973.
DOI : 10.1145/321738.321743

A. M. Lyapunov, General Problem of the Stability Of Motion, 1992.

T. Marconi, Y. Lu, K. Bertels, and G. Gaydadjiev, A novel fast online placement algorithm on 2D partially reconfigurable devices, 2009 International Conference on Field-Programmable Technology, pp.296-299, 2009.
DOI : 10.1109/FPT.2009.5377661

W. S. Mcculloch and W. Pitts, A logical calculus of the ideas immanent in nervous activity, Bulletin of Mathematical Biology, vol.5, issue.4, pp.115-133, 1943.

A. Pasturel, A. Eiche, D. Chillet, S. Pillement, and O. Sentieys, Implémentation matérielle d'un réseau de neurones pour l'ordonnancement temporel de tâches sur architectures multi-processeur hétérogènes Dart : a functional-level reconfigurable architecture for high energy efficiency, Symposium en Architecture de machines (SympA), pp.1-513, 2008.

N. Pullman, Clique coverings of graphs ??? A survey, Combinatorial Mathematics X Lecture Notes in Mathematics, vol.33, pp.72-85, 1983.
DOI : 10.1016/0097-3165(73)90065-4

F. Rosenblatt, The perceptron: A probabilistic model for information storage and organization in the brain., Psychological Review, vol.65, issue.6, p.386, 1958.
DOI : 10.1037/h0042519

C. Rossmeissl, A. Sreeramareddy, and A. Akoglu, Partial Bitstream 2-D Core Relocation for Reconfigurable Architectures, 2009 NASA/ESA Conference on Adaptive Hardware and Systems, pp.98-105, 2009.
DOI : 10.1109/AHS.2009.41

K. Rupnow, W. Fu, and K. Compton, Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, pp.63-70, 2009.
DOI : 10.1109/FCCM.2009.30

K. Schild and J. Würtz, Off-line scheduling of a real-time system, Proceedings of the 1998 ACM symposium on Applied Computing , SAC '98, pp.29-38, 1998.
DOI : 10.1145/330560.330566

J. B. Sidney, Optimal Single-Machine Scheduling with Earliness and Tardiness Penalties, Operations Research, vol.25, issue.1, pp.62-69, 1977.
DOI : 10.1287/opre.25.1.62

H. T. Siegelmann and E. D. Sontag, Turing computability with neural nets, Applied Mathematics Letters, vol.4, issue.6, pp.77-80, 1991.
DOI : 10.1016/0893-9659(91)90080-F

C. Steiger, H. Walder, and M. Platzner, Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks, IEEE Transactions on Computers, vol.53, issue.11, pp.1393-1407, 2004.
DOI : 10.1109/TC.2004.99

J. Tabero, J. Septien, H. Mecha, and D. Mozos, A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management, 14th International Conference Field-programmable logic and applications, pp.241-250, 2004.
DOI : 10.1007/978-3-540-30117-2_26

G. Tagliarini, E. Christ, and . Page, Optimization using neural networks, IEEE Transactions on Computers, vol.40, issue.12, pp.1347-1358, 1991.
DOI : 10.1109/12.106220

A. Tanenbaum, J. A. Hernandez, R. Joly, and M. Dupuy, Systèmes d'exploitation, 2003.

H. Walder, C. Steiger, and M. Platzner, Fast online task placement on FPGAs: free space partitioning and 2D-hashing, Proceedings International Parallel and Distributed Processing Symposium, 2003.
DOI : 10.1109/IPDPS.2003.1213329

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.5.2519

. Xilinx, Early Access Partial Reconfiguration User Guide, 2006.

. Xilinx, Virtex-4 FPGA Configuration User Guide (UG071 v1.11), 2009.

. Xilinx, Virtex-5 FPGA Configuration User Guide (UG191 v3.10), 2011.

J. Xu and D. Parnas, Scheduling processes with release times, deadlines, precedence and exclusion relations, IEEE Transactions on Software Engineering, vol.16, issue.3, pp.360-369, 1990.
DOI : 10.1109/32.48943

Z. Zhou and S. Chen, Evolving Fault-Tolerant Neural Networks, Neural Computing & Applications, vol.11, issue.3-4, pp.156-160, 1007.
DOI : 10.1007/s00521-003-0353-4

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.19.1117

.. Fpga-reconfigurable-dynamiquement-par-colonne, Un module M 1 est exécuté sur lapremì ere colonne, p.16

F. Reconfiguration-par-région, La sous figure (a) présente un FPGA composé de cinq régions La sous figure (b) illustre l'exécution de deux modules sur ce, p.16

. Fpga-reconfigurable-dynamiquement-par-colonne, Trois tâches sont en cours d'exécution sur le FPGA. L'espace libre restant est la colonne C 2, p.29

. Exemple-de-motifs-soumis-au-réseau, Les pixels de chaque motif sont numérotés de unàunà neuf et les motifs sont numérotés de unàunà trois, p.41

.. Diagramme-de-gantt-de-l, exécution des huit tâches décrites par l'´ equation (3.15) sur une architecture disposant de quatre unités d'exécution. (a) Solution obtenue par l'algorithme Pfair. (b) Solution obtenue par notre algorithme, p.70

.. Exemple-d-'une-matrice-de-connexion, LesélémentsLeséléments diagonaux ont des valeurségalesàvaleurségalesvaleurségalesà zéro tandis que les autres elements w ij sont négatifs ou nuls, p.119

.. Les-sous-figures, (b) et (c) décrivent le placement successif des tâches ? 1 , ? 2 et ? 3 . La sous-figure (d) représente le placement optimal en termes de nombre de rectangles vides, p.137