A. Ahmadi and M. Zwolinski, Word-Length Oriented Multiobjective Optimization of Area and Power Consumption in DSP Algorithm Implementation, 2006 25th International Conference on Microelectronics, pp.614-617, 2006.
DOI : 10.1109/ICMEL.2006.1651042

T. Arslan and D. H. Horrocks, A genetic algorithm for the design of finite word length arbitrary response cascaded IIR digital filters, 1st International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA), pp.276-281, 1995.
DOI : 10.1049/cp:19951062

G. Baicher, Optimization of Finite Word Length Coefficient IIR Digital Filters Through Genetic Algorithms ??? A Comparative Study, Advances in Natural Computation , 4222 of Lecture Notes in Computer Science, pp.641-650, 2006.
DOI : 10.1007/11881223_79

A. Banciu, E. Casseau, D. Menard, and T. Michel, Stochastic modeling for floating-point to fixed-point conversion, 2011 IEEE Workshop on Signal Processing Systems (SiPS), pp.180-185, 2011.
DOI : 10.1109/SiPS.2011.6088971

URL : https://hal.archives-ouvertes.fr/hal-00746791

P. H. Bauer and L. Leclerc, A computer-aided test for the absence of limit cycles in fixed-point digital filters, IEEE Transactions on Signal Processing, vol.39, issue.11, pp.392400-2410, 1991.
DOI : 10.1109/78.97995

P. Belanovic and M. Lesser, A Library of Parameterized Floating-Point Modules and Their Use, International Conference on Field Programmable Logic and Applications, FPL2002, pp.657-666, 2002.
DOI : 10.1007/3-540-46117-5_68

F. Berens and N. Naser, Algorithm to system-on-chip design flow that leverages system-studio and systemc, p.22, 2004.

. Bluespec, Bluespec compiler

D. Boland and G. A. Constantinides, Bounding variable values and roundoff effects using handelman representations. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.30, issue.11, pp.1691-1704, 2011.

T. Bose and M. Chen, Overflow oscillations in state-space digital filters. Circuits and Systems, IEEE Transactions on, vol.38, issue.7, pp.807-810, 1991.

T. Bose and M. Chen, Stability of digital filters implemented with two's complement truncation quantization, IEEE Transactions on Signal Processing, vol.40, issue.1, pp.24-31, 1929.
DOI : 10.1109/78.157178

S. P. Boyd and L. Vandenberghe, Convex Optimization, p.178, 2004.

G. Caffarena, C. Carreras, J. A. López, and . Fernández, SQNR Estimation of Fixed-Point DSP Algorithms, EURASIP Journal on Advances in Signal Processing, vol.2010, issue.1, pp.1-2112, 2010.
DOI : 10.1109/TCSI.2004.823652

G. Caffarena, J. A. López, G. Leyva, C. Carreras, and O. Nieto-taladriz, Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs, International Journal of Reconfigurable Computing, vol.8, issue.3, pp.1-8, 1921.
DOI : 10.1109/82.868453

G. Caffarena, J. A. López, G. Leyva, C. Carreras, and O. Nieto-taladriz, Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs, International Journal of Reconfigurable Computing, vol.8, issue.3, pp.1-8, 1929.
DOI : 10.1109/82.868453

J. D. Campo, F. Cruz-roldan, and M. Utrilla-manso, Tighter limit cycle bounds for digital filters, IEEE Signal Processing Letters, vol.13, issue.3, pp.13149-152, 2006.
DOI : 10.1109/LSP.2005.862606

M. Cantin, Y. Savaria, and P. Lavoie, A comparison of automatic word length optimization procedures, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), pp.612-615, 2002.
DOI : 10.1109/ISCAS.2002.1011427

M. Cantin, Y. Savaria, D. Prodanos, and P. Lavoie, An automatic word length determination method, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), pp.53-56, 2001.
DOI : 10.1109/ISCAS.2001.921982

C. Carreras, J. A. Lopez, and O. Nieto-taladriz, Bit-width selection for data-path implementations, Proceedings 12th International Symposium on System Synthesis, pp.114-119, 1999.
DOI : 10.1109/ISSS.1999.814269

F. Catthoor, H. De-man, and J. Vandewalle, Simulated-annealing-based optimization of coefficient and data word-lengths in digital filters, International Journal of Circuit Theory and Applications, vol.40, issue.4, pp.16371-390, 1988.
DOI : 10.1002/cta.4490160404

S. C. Chan and K. M. Tsui, Wordlength Determination Algorithms for Hardware Implementation of Linear Time Invariant Systems with Prescribed Output Accuracy, 2005 IEEE International Symposium on Circuits and Systems, pp.2607-2610, 2005.
DOI : 10.1109/ISCAS.2005.1465160

S. C. Chan and K. M. Tsui, Wordlength Optimization of Linear Time-Invariant Systems With Multiple Outputs Using Geometric Programming, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, issue.4, pp.54845-854, 2007.
DOI : 10.1109/TCSI.2006.888769

H. Choi and W. P. Burleson, Search-based wordlength optimization for VLSI/DSP synthesis, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing, pp.198-207, 1994.
DOI : 10.1109/VLSISP.1994.574744

A. Cilio and H. Corporaal, Floating Point to Fixed Point Conversion of C Code, Lecture Notes in Computer Science, vol.1575, pp.1-99, 1999.
DOI : 10.1007/978-3-540-49051-7_16

T. Claasen, W. Mecklenbrauker, and J. Peek, Effects of quantization and overflow in recursive digital filters. Acoustics, Speech and Signal Processing, IEEE Transactions, issue.6, pp.24517-529, 1976.

M. Clark, M. Mulligan, D. Jackson, and D. Linebarger, Accelerating Fixed-Point Design for MB-OFDM UWB Systems, CommsDesign, 2004.

J. A. Clarke, G. A. Constantinides, and P. Y. Cheung, Word-length selection for power minimization via nonlinear optimization, ACM Transactions on Design Automation of Electronic Systems, vol.14, issue.3, pp.1-3928, 2009.
DOI : 10.1145/1529255.1529261

R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, and I. Bolsens, A methodology and design environment for dsp asic fixed point refinement, Proceedings of the conference on Design, automation and test in Europe, DATE '99, p.37, 1999.

J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang et al., Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, pp.231-234, 2009.
DOI : 10.1109/FCCM.2009.35

G. A. Constantinides, Perturbation analysis for word-length optimization, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., p.26, 2003.
DOI : 10.1109/FPGA.2003.1227244

G. A. Constantinides, P. Y. Cheung, and W. Luk, Wordlength optimization for linear digital signal processing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22, issue.10, pp.1432-1442, 2003.
DOI : 10.1109/TCAD.2003.818119

G. A. Constantinides, P. Y. Cheung, and L. Wayne, Synthesis and Optimization of DSP Algorithms, p.39, 2004.

G. A. Constantinides, Y. K. Peter, W. Cheung, and . Luk, Multiple precision for resource minimization, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), p.307, 2000.
DOI : 10.1109/FPGA.2000.903430

G. A. Constantinides and G. Woeginger, The complexity of multiple wordlength assignment, Applied Mathematics Letters, vol.15, issue.2, pp.137-140, 2002.
DOI : 10.1016/S0893-9659(01)00107-0

. Coware, Coware spw, 1921.

D. Novo-bruna, Exploiting adaptive precision in software defined radios. Doctoral dissertation, p.39, 2010.

L. De-coster, M. Ade, R. Lauwereins, and J. Peperstraete, Code generation for compiled bit-true simulation of DSP applications, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210), pp.9-14, 1998.
DOI : 10.1109/ISSS.1998.730590

F. De-dinechin, C. Klein, and B. Pasca, Generating high-performance custom floating-point pipelines, 2009 International Conference on Field Programmable Logic and Applications, pp.59-64, 2009.
DOI : 10.1109/FPL.2009.5272553

URL : https://hal.archives-ouvertes.fr/ensl-00379154

J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, pp.127-144, 1921.
DOI : 10.1109/JPROC.2002.805829

C. Ewe, P. Cheung, and G. A. Constantinides, Error modeling of dual fixed-point arithmetic and its application in field programmable logic, International Conference on Field Programmable Logic and Applications, FPL2005, pp.124-129, 2005.

C. Fang-fang, R. A. Rutenbar, M. Püschel, and T. Chen, Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling, Proceedings of the 40th conference on Design automation , DAC '03, pp.496-501, 2003.
DOI : 10.1145/775832.775960

P. D. Fiore, Efficient Approximate Wordlength Optimization, IEEE Transactions on Computers, vol.57, issue.11, pp.1561-1570, 2008.
DOI : 10.1109/TC.2008.87

P. D. Fiore and L. Lee, Closed-form and real-time wordlength adaptation, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258), pp.1897-1932, 1900.
DOI : 10.1109/ICASSP.1999.758294

A. Gaffar, O. Mencer, W. Luk, P. Cheung, and N. Shirazi, Floatingpoint bit-width analysis via automatic differentiation, International Conference on Field Programmable Logic and Applications, FPL2002, pp.158-165, 2002.

. Gecos, Generic compiler suite, p.38

M. C. Grant, S. P. Stephen, and P. B. Boyd, The CVX Users Guide, 0190.

K. Han, Automating transformations from oating-point to xedpoint for implementing digital signal processing algorithms, p.35, 2006.

K. Han and B. L. Evans, Optimum Wordlength Search Using Sensitivity Information, EURASIP Journal on Advances in Signal Processing, vol.51, issue.1, pp.76-76, 2006.
DOI : 10.1155/ASP/2006/92849

K. Han, I. Eo, K. Kim, and H. Cho, Numerical word-length optimization for cdma demodulator, The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, pp.290-293, 1933.

C. He, G. Qin, M. Lu, and W. Zhao, An efficient implementation of highaccuracy finite difference computing engine on fpgas, International Conference on Application Specific Systems, Architectures and Processors, pp.95-98, 2006.

S. He and M. Torkelson, Designing pipeline fft processor for ofdm (de)modulation, Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on, pp.257-262, 1998.

N. Herve, Contributions la synthse d'architecture virgule fixe largeurs multiples Doctoral thesis, University of Rennes-1, p.175, 2007.

T. Hinamoto, S. Yokoyama, T. Inoue, W. Zeng, and W. Lu, Analysis and minimization of l2-sensitivity for linear systems and two-dimensional state-space filters using general controllability and observability gramians, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, pp.491279-1289, 1928.

C. H. Ho, C. W. Yu, P. Leong, W. Luk, and S. Wilton, Floating-point fpga: Architecture and modeling, IEEE. Transactions on Very Large Scale Integration Systems, pp.1709-1718, 2009.

A. Inc, Apple macbook pro, version 10.5.8, p.194, 2008.

L. B. Jackson, On the interaction of roundoff noise and dynamic range in digital filters. The Bell System Technical Journal, p.49, 1970.

M. Jersak and M. Willems, Fixed-point extended c compiler allows more efficient high-level programming of fixed-point dsps, Proceedings of the International Conference on Signal Processing Applications and Technology ICSPAT 1998, pp.1-5, 1998.

G. E. Johnson, Constructions of particular random processes, Proceedings of the IEEE, vol.82, issue.2, pp.270-285, 1994.
DOI : 10.1109/5.265353

K. Kalliojarvi and J. Astola, Roundoff errors in block-floating-point systems, IEEE Transactions on Signal Processing, vol.44, issue.4, pp.44783-790, 1996.
DOI : 10.1109/78.492531

J. Kauraniemi, Analysis of limit cycles in the direct form delta operator structure by computer-aided test, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.2177-2180, 1997.
DOI : 10.1109/ICASSP.1997.599480

H. Keding, Pain killers for fixed-point design flow, 1921.

H. Keding, M. Coors, O. Lüthje, and H. Meyr, Fast bit-true simulation, Proceedings of the 38th conference on Design automation , DAC '01, pp.708-713, 2001.
DOI : 10.1145/378239.379052

J. F. Kenny and E. S. Keeping, Cumulants and the cumulant-generating function, additive property of cumulants, and sheppards correction, Mathematics of Statistics, pp.77-82, 1951.

S. Kim, . Ki-il, W. Kum, and . Sung, Fixed-point optimization utility for C and C++ based digital signal processing programs, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp.1455-1464, 1998.

S. Kim and W. Sung, Fixed-point-Simulation Utility for C and C++BasedDigitalSignalProcessingPrograms, Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, pp.162-166, 1994.

S. Kim and W. Sung, A floating-point to fixed-point assembly program translator for the TMS320C25, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp.41730-739, 1994.

R. R. Kinnison, Applied Extreme Value Statistics, p.20, 1985.
DOI : 10.2172/6045789

K. I. Kum and W. Sung, Combined word-length optimization and high-level synthesis of digital signal processing systems, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, issue.8, pp.20921-930, 2001.

D. Lee, A. A. Gaffar, R. C. Cheung, O. Mencer, W. Luk et al., Accuracy-Guaranteed Bit-Width Optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.10, pp.251990-2000, 2006.
DOI : 10.1109/TCAD.2006.873887

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.6194

D. Lee, A. A. Gaffar, R. C. Cheung, O. Mencer, W. Luk et al., Accuracy-Guaranteed Bit-Width Optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.10, pp.251990-2000, 2006.
DOI : 10.1109/TCAD.2006.873887

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.6194

D. Lee, A. A. Gaffar, O. Mencer, and W. Luk, MiniBit, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.837-840, 2005.
DOI : 10.1145/1065579.1065799

J. Lee, R. Haralick, and L. Shapiro, Morphologic edge detection Robotics and Automation, IEEE Journal, vol.3, issue.2, pp.142-156, 1987.

G. Li, M. Gevers, and S. Youxian, Performance analysis of a new structure for digital filter implementation IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, pp.47474-482, 1928.

M. Li, B. Bougard, E. E. Lopez, A. Bourdoux, D. Novo et al., Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures, 2008 IEEE International Conference on Communications, pp.737-741, 2008.
DOI : 10.1109/ICC.2008.144

J. A. López, G. Caffarena, and C. Carreras, Fast and accurate computation of l2 sensitivity in digital filter realizations, p.29, 2006.

J. A. Lopez, G. Caffarena, C. Carreras, and O. Nieto-taladriz, Analysis of limit cycles by means of affine arithmetic computer-aided tests, 12th European Signal Processing Conference, pp.991-994, 2004.

J. A. Lopez, G. Caffarena, C. Carreras, and O. Nieto-taladriz, Fast and accurate computation of the roundoff noise of linear time-invariant systems, IET Circuits, Devices Systems, pp.393-408, 2008.

J. A. Lopez, C. Carreras, G. Caffarena, and O. Nieto-taladriz, Fast characterization of the noise bounds derived from coefficient and signal quantization, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.309-312, 2003.
DOI : 10.1109/ISCAS.2003.1205835

J. A. Lopez, C. Carreras, and O. Nieto-taladriz, Improved interval-based characterization of fixed-point lti systems with feedback loops. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.19, issue.11, pp.261923-1933, 2007.

. Mathworks, Fixed-point blockset user's guide (ver. 2.0), 1921.

P. K. Meher, J. Valls, T. Juang, K. Sridharan, and K. Maharatna, 50 years of cordic: Algorithms, architectures, and applications. Circuits and Systems I: Regular Papers, IEEE Transactions, issue.9, pp.561893-1907, 2009.

D. Menard and . Id, fix -infrastructure for the design of fixed-point systems, University Booth of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), p.38, 2011.

D. Menard, D. Chillet, and O. Sentieys, Floating-to-Fixed-Point Conversion for Digital Signal Processors, EURASIP Journal on Applied Signal Processing, vol.37, issue.8, pp.1-19, 2006.
DOI : 10.1155/ASP/2006/96421

URL : https://hal.archives-ouvertes.fr/inria-00459212

D. Menard, R. Rocher, and O. Sentieys, Analytical fixed-point accuracy evaluation in linear time-invariant systems. Circuits and Systems I: Regular Papers, IEEE Transactions, issue.10, pp.553197-3208, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00459231

D. Menard and O. Sentieys, Automatic evaluation of the accuracy of fixedpoint algorithms, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp.529-535, 2002.
URL : https://hal.archives-ouvertes.fr/inria-00482931

W. Mills, C. Mullis, and R. Roberts, Digital filter realizations without overflow oscillations, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.26, issue.4, pp.334-338, 1978.
DOI : 10.1109/TASSP.1978.1163114

S. K. Mitra, Digital Signal Processing Laboratory Using MATLAB, p.159, 1999.

R. E. Moore, Inerval Analysis, p.18, 1966.

R. Nambiar, C. K. Tang, and P. Mars, Genetic and learning automata algorithms for adaptive digital filters, [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.41-44, 1992.
DOI : 10.1109/ICASSP.1992.226416

A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.722-728, 2001.
DOI : 10.1109/DATE.2001.915108

M. Nemani and F. N. Najm, High-level area and power estimation for VLSI circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.6, pp.697-713, 1999.
DOI : 10.1109/43.766722

S. C. Ng, S. H. Leung, C. Y. Chung, A. Luk, and W. H. Lau, The genetic search approach. A new learning algorithm for adaptive IIR filtering, IEEE Signal Processing Magazine, vol.13, issue.6, pp.1338-1384, 1996.
DOI : 10.1109/79.543974

H. Nguyen, D. Menard, and O. Sentieys, Novel algorithms for wordlength optimization, 19th European Signal Processing Conference, pp.1944-1948, 2011.

Z. Ning, B. Haller, and R. Brodersen, Systematic architecture exploration for implementing interference suppression techniques in wireless receivers, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), pp.218-227, 2000.
DOI : 10.1109/SIPS.2000.886719

M. Novey, T. Adali, and A. Roy, A Complex Generalized Gaussian Distribution— Characterization, Generation, and Estimation, IEEE Transactions on Signal Processing, vol.58, issue.3, pp.1427-1433, 2010.
DOI : 10.1109/TSP.2009.2036049

D. Novo, A. Kritikakou, P. Raghavan, L. Van-der-perre, J. Huisken et al., Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance, 2010 IEEE 8th Symposium on Application Specific Processors (SASP), pp.30-35, 2010.
DOI : 10.1109/SASP.2010.5521151

A. Oppenheim-emrë, A. P. Ozer, D. G. Nisbet, A. P. Ozer, D. Nisbet et al., A stochastic bitwidth estimation technique for compact and low-power custom processors A stochastic bitwidth estimation technique for compact and low-power custom processors, ACM Transactions on Embedded Computer Systems ACM Transactions on Embedded Computer Systems, vol.181013430102, issue.7, pp.18130-1361, 1970.

K. Keshab and . Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, p.118, 1999.

T. Peli and D. Malah, A study of edge detection algorithms, Computer Graphics and Image Processing, vol.20, issue.1, pp.1-21, 1982.
DOI : 10.1016/0146-664X(82)90070-3

K. Peppas, F. Lazarakis, D. Axiotis, T. Gizawi, and A. Alexandridis, System level performance evaluation of MIMO and SISO OFDM-based WLANs, Wireless Networks, vol.62, issue.2, pp.859-873, 2009.
DOI : 10.1007/s11276-007-0079-9

K. Premaratne, E. C. Kulasekere, P. H. Bauer, and L. J. Leclerc, An exhaustive search algorithm for checking limit cycle behavior of digital filters, IEEE International Symposium on Circuits and Systems, pp.2035-2038, 1995.

R. Rocher, D. Menard, P. Scalart, and O. Sentieys, Analytical accuracy evaluation of fixed-point systems, 15th European Signal Processing Conference, pp.999-1003, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00454534

R. Rocher, D. Menard, N. Herve, and O. Sentieys, Fixed-point configurable hardware components, EURASIP Journal on Embedded Systems, issue.1, pp.1-13, 1921.
DOI : 10.1186/1687-3963-2006-023197

URL : https://hal.archives-ouvertes.fr/inria-00455557

A. Savich, M. Moussa, and S. Areibi, The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study, IEEE Transactions on Neural Networks, vol.18, issue.1, pp.240-252, 2007.
DOI : 10.1109/TNN.2006.883002

C. Shi and R. W. Brodersen, Automated fixed-point data-type optimization tool for signal processing and communication systems, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.478-483, 2004.
DOI : 10.1145/996566.996700

C. Shi and R. W. Brodersen, A perturbation theory on statistical quantization effects in fixed-point dsp with non-stationary inputs, Proceedings of the 2004 International Symposium on Circuits and Systems, pp.373-379, 1928.

Y. Frank and . Shih, Image Processing and Mathematical Morphology: Fundamentals and Applications, p.131, 2009.

N. Sulaiman, A multi-objective genetic algorithm for on-chip real-time optimisation of word length and power consumption in a pipelined FFT processor targeting a MC-CDMA receiver, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05), pp.154-159, 2005.
DOI : 10.1109/EH.2005.4

W. Sung and K. Ki, Word-length determination and scaling software for a signal flow block diagram ICASSP-94, Acoustics, Speech, and Signal Processing IEEE International Conference on, ii, pp.457-489, 1994.

W. Sung and K. Kum, Simulation-based word-length optimization method for fixed-point digital signal processing systems, dec 1995. 33 REFERENCES [117] Synopsys. Synopsys prime time suite, pp.433087-3090

P. Vaidyanathan and V. Liu, An improved sufficient condition for absence of limit cycles in digital filters, IEEE Transactions on Circuits and Systems, vol.34, issue.3, pp.319-322, 1987.
DOI : 10.1109/TCS.1987.1086118

J. Weijers, V. Derudder, S. Janssens, F. Petré, and A. Bourdoux, From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow, EURASIP Journal on Advances in Signal Processing, vol.16, issue.8, pp.138-138, 2006.
DOI : 10.1155/ASP/2006/39297

B. Widrow and I. Kollár, Quantization Noise: Roundoff Error in Digital Computation, Signal Processing, Control, and Communications, pp.86-100, 2008.
DOI : 10.1017/CBO9780511754661

M. Willems, V. Bursgens, T. Grotker, and H. Meyr, FRIDGE: an interactive code generation environment for HW/SW codesign, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp.287-290, 1997.
DOI : 10.1109/ICASSP.1997.599625

P. W. Wolniansky, G. J. Foschini, G. D. Golden, and R. A. Valenzuela, V-BLAST: an architecture for realizing very high data rates over the rich-scattering wireless channel, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), pp.295-300, 1998.
DOI : 10.1109/ISSSE.1998.738086

. Xilinx, System generator for dsp

C. W. Yu, J. Lamoureux, S. Wilton, P. Leong, and W. Luk, The coarsegrained/ fine-grained logic interface in fpgas with embedded floating-point arithmetic, International Journal of Reconfigurable Computing, pp.1-10, 2008.