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Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée

Abstract : Partially depleted SOI technologies (PD-SOI), offer advantages in terms of speed and dynamic power consumption compared to bulk technologies. The main drawback of the PD-SOI technology is its static power consumption, which is higher than bulk one. It is due to the floating body of its transistors. This work presents a new static power consumption design technique based on power switches. A new factor of merit is introduced selecting the power switch with the best trade-off in terms of leakage current, speed and area. A new power switch brings, in comparison to a reference solution, a reduction of 20% of the ON mode equivalent resistance for the same OFF mode leakage current PD-SOI Silicon validation test chips include LDPC bloc supplied by the proposed solution. Comparing to the bulk technology, a speed gain of 20% is measured for the same voltage supply and a dynamic power consumption reduction of 30% at same speed is achieved. This solution allows reducing by 2 the static power consumption. Finally, a retention flip-flop associated to the implementation of power switches and optimized in PD-SOI is proposed. This flip-flop is designed to be robust with a low leakage current.
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Julien Le Coz. Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée. Autre. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT076⟩. ⟨tel-00764400⟩

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