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Etude et modélisation compacte du transistor FinFET ultime

Abstract : One of the main technological solutions related to downscaling of CMOS technology is now clearly oriented to lightly doped multigate MOSFETs. They offer better immunity against short channel effects compared to planar bulk MOSFETs (see ITRS 2011). Among the multigate MOSFETs, the SOI FinFET transistor is an interesting candidate because of the similarity of its manufacturing process with the planar transistor technology. In parallel, there is a real expectation on the part of designers and foundries to have compact models numerically efficient, accurate and close to the physics, and then inserted in to the design tools in order to study and develop ambitious circuits in FinFET technology. This thesis focuses on the development of a design-oriented compact model of FinFET transistor valid to nanoscale dimensions. This model takes into account the short channel effects, the channel length modulation, the mobility degradation, the quantum mechanic effects and the transcapacitances. A validation of this model is carried out by comparisons with 3DTCAD simulations. The compact model is implemented in Verilog-A to simulate innovative FinFET-based circuits. A gate-level modeling is developed for the simulation of complex digital circuits. This thesis also presents a generic compact modeling of multigate SOI MOSFETs with lightly doped channels and temperature dependent. According to a concept of geometric transformation, our compact model of the planar double-gate MOSFET is extended to be applied to any other type of multigate MOSFETs (MuGFET). An experimental validation of the MuGFET compact model with a triple gate transistor is proposed. This thesis finally brings solutions for the modeling of junction less double-gate MOSFET.
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https://tel.archives-ouvertes.fr/tel-00750928
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Submitted on : Monday, November 19, 2012 - 1:21:19 PM
Last modification on : Wednesday, August 22, 2018 - 1:22:04 PM
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Nicolas Chevillon. Etude et modélisation compacte du transistor FinFET ultime. Micro et nanotechnologies/Microélectronique. Université de Strasbourg, 2012. Français. ⟨NNT : 2012STRAD016⟩. ⟨tel-00750928⟩

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