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Analyse du temps d'exécution pire-cas de tâches temps-réel exécutées sur une architecture multi-cœurs

Abstract : Software failures in hard real-time systems may have hazardous effects (industrial disasters, human lives endangering). The verification of timing constraints in a hard real-time system depends on the knowledge of the worst-case execution times (WCET) of the tasks accounting for the embedded program. Using multicore processors is a mean to improve embedded systems performances. However, determining worst-case execution times estimates on these architectures is made difficult by the sharing of some resources among cores, especially the interconnection bus that enables accesses to the shared memory. This document proposes a two-level arbitration scheme that makes it possible to improve executed tasks performances while complying with timing constraints. Described methods assess an optimal bus access priority level to each of the tasks. They also allow to find an optimal allocation of tasks to cores when tasks to execute are more numerous than available cores. Experimental results show a meaningful drop in worst-case execution times estimates and processor utilization.
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https://tel.archives-ouvertes.fr/tel-00746073
Contributor : Roman Bourgade Connect in order to contact the contributor
Submitted on : Friday, October 26, 2012 - 9:40:06 PM
Last modification on : Monday, July 4, 2022 - 9:29:24 AM
Long-term archiving on: : Sunday, January 27, 2013 - 3:50:36 AM

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  • HAL Id : tel-00746073, version 1

Citation

Roman Bourgade. Analyse du temps d'exécution pire-cas de tâches temps-réel exécutées sur une architecture multi-cœurs. Architectures Matérielles [cs.AR]. Université Paul Sabatier - Toulouse III, 2012. Français. ⟨NNT : ⟩. ⟨tel-00746073⟩

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