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Compilation optimisante pour processeurs extensibles

Antoine Floc'H 1 
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Application specific instruction set processors (ASIP) are a well known compromise between the high performance of a dedicated hardware and the flexibility of a programmable processor. These specialized processors may be composed of a general purpose processor whose instruction set is extended by instructions that are specific to one or few applications. Such specific instructions will be executed on a dedicated hardware extension that will reduce their execution times. If the design and verification cost of an extensible processor is reduced compared to a from scratch hardware design, the complexity is partly transferred to the compilation step. Indeed, the instruction set of an extensible processor is both an input and an output of the compilation process. This singularity implies a questioning of the compilation itself and usually place the designer at the heart of an iterative and exploration based design process. This thesis proposes several contributions to guide the design process of an extensible processor through automated optimization techniques. The first of these contributions is to select and schedule custom VLIW instructions by solving a single constraint programming (CP) optimization problem. Furthermore, we propose a novel technique that addresses the interactions between code optimization and instruction set extesion. The idea is to automatically transform the original loop nests of program (using the polyhedral model) to select specialized and vectorisables instructions. These instructions may use local memories of the hardware extension to store intermediates data produced at a given loop iteration.
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Submitted on : Thursday, August 30, 2012 - 10:21:12 AM
Last modification on : Wednesday, February 2, 2022 - 11:54:24 AM
Long-term archiving on: : Friday, December 16, 2016 - 9:04:59 AM


  • HAL Id : tel-00726420, version 1


Antoine Floc'H. Compilation optimisante pour processeurs extensibles. Architectures Matérielles [cs.AR]. Université Rennes 1, 2012. Français. ⟨tel-00726420⟩



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