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Etude physique et technologique d'architectures de transistors MOS à nanofils

Abstract : This thesis is titled “A Study on Carrier Transport Properties of Vertically-Stacked Nanowire Transistors,” and is organized in seven chapters in English.   Gate-all-around (GAA) silicon nanowire transistors (SNWTs) are one of the best structures to suppress short channel effect for future CMOS devices. In addition, vertically-stacked channel structure benefits from high on-state current owing to reduced footprint. In this thesis, the carrier transport properties of vertically-stacked GAA SNWTs have been experimentally investigated. The vertically-stacked GAA SNWTs were fabricated on SOI wafers by selective etching of SiGe layers in epitaxially-grown Si/SiGe superlattice and top-down CMOS process. The experimental results reveal stacked-channel structure can achieve superior on-state current. It was also found that the effective mobility decreases with diminishing nanowire cross-section width from 30 nm down to 5 nm. This study gives basis and guidelines to optimize the performance of GAA SNWTs for future CMOS devices.
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Submitted on : Tuesday, July 31, 2012 - 11:07:58 AM
Last modification on : Friday, March 25, 2022 - 9:40:23 AM
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  • HAL Id : tel-00721968, version 1



Kiichi Tachi. Etude physique et technologique d'architectures de transistors MOS à nanofils. Micro et nanotechnologies/Microélectronique. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT084⟩. ⟨tel-00721968⟩



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