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Caractérisation de transport des électrons dans les transistors MOS à canal court

Abstract : Electron transport is one of the key properties that need to be improved in order to sustain performance improvement for the next technological nodes. Many factors, such as the choice of gate stack materials, channel material or the presence of mechanical strain contribute to degrade or improve transport properties. Body thickness, which reaches dimensions of a few nanometers, is playing a role as well, through interface scattering, thickness fluctuations or electrostatic and quantum coupling effects between front and back interfaces. In addition, it is strongly suspected that additional scattering mechanisms are associated with the proximity of the highly doped source and drain regions. For the sake of sub 32nm technology nodes development, it is of fundamental importance that these various mechanisms be identified and studied. In this range of dimensions, electron transport is governed by out of equilibrium, or even ballistic, phenomena. Therefore along with the advancement in the technology nodes, it becomes necessary to evolve the transport models and parameters to better explain the MOSFET operation. This thesis focuses on understanding the existing transport models and extraction methods and improving the same under the context of current and future technology nodes mainly sub 32nm. The MOSFET transport models and static parameter extraction methods in linear and saturation regime have been explored during the course of this thesis. The impact of gate voltage dependent series resistance in the advanced MOSFETs is taken into account and a new improved extraction method has being developed in the linear regime. Low temperature measurement is used in linear regime for the extraction of scattering mechanisms using mobility model. A new saturation drain current correction for short channel MOSFETs is developed for taking into account both DIBL and self-heating using low temperature measurement. Velocity saturation vsats model and extraction method is explored in the saturation regime and vsats is studied against temperature and channel lengths. Ballistic and quasi ballistic model with concept of kT layer in saturation regime is also studied for the sake of sub 32nm nodes. Channel magnetoresistance measurement offers promising prospects for short channel devices as we can directly extract the channel mobility without the need for the knowledge of channel dimensions. An analytical magnetoresistance model is developed in the context of sub 32nm technology nodes for full ballistic and quasi ballistic transport models. Magnetoresistance measurement is explored in the saturation region for the first time down to 50nm on bulk MOSFETs in order to understand the applicability of this extraction method in this regime. Finally Bulk+ FDSON, FinFET, and GAA devices are characterized with temperature and studied the transport mechanism in these novel devices down to 35nm (FinFET). Also effective field parameter η is extracted for sSOI devices and found that this is significantly different from bulk value as in the case of previous results in strained bulk and FDSOI devices and this is interpreted as increased surface roughness and phonon scattering due to preferential sub band occupation in these advanced devices.
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Submitted on : Wednesday, July 25, 2012 - 11:22:14 AM
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Narasimhamoorthy Subramanian. Caractérisation de transport des électrons dans les transistors MOS à canal court. Autre. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT093⟩. ⟨tel-00720613⟩



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