R. Rocher, D. Ménard, P. Scalar, and &. O. Sentieys, General Model for Analytical Evaluation of Fixedpoint systems. Accepted for publication in IEEE Transactions on Circuits and Systems I, 2012, pp.22-28

]. M. Alam-12a, O. Alam, D. Berder, O. Ménard, and T. Sentieys, TAD-MAC: Traffic-Aware Dynamic MAC Protocol for Wireless Body Area Sensor Networks, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.2, issue.1, pp.99-71, 2012.
DOI : 10.1109/JETCAS.2012.2187243

D. Ménard, N. Hervé, O. Sentieys, and &. Nguyen, High-Level Synthesis under Fixed-Point Accuracy Constraint, Journal of Electrical and Computer Engineering, vol.1, issue.3, p.57, 2012.
DOI : 10.1109/TCAD.2003.818119

G. Caffarena, O. Sentieys, D. Ménard, J. A. López, and D. Novo, Quantization of VLSI digital signal processing systems, EURASIP Journal on Advances in Signal Processing, vol.2012, issue.1, pp.32-37, 2012.
DOI : 10.1186/1687-6180-2012-32

URL : https://hal.archives-ouvertes.fr/hal-00743410

]. M. Alam-11a, O. Alam, D. Berder, T. Ménard, &. O. Anger et al., A Hybrid Model for Accurate Energy Analysis of WSN Nodes, EURASIP Journal on Embedded Systems, vol.19, issue.5, pp.14-72, 2011.
DOI : 10.1109/SURV.2010.020510.00058

R. Rocher, D. Ménard, O. Sentieys, and &. P. Scalart, Accuracy evaluation of fixed-point based LMS algorithm, Digital Signal Processing, vol.20, issue.3, pp.640-652, 2010.
DOI : 10.1016/j.dsp.2009.10.007

URL : https://hal.archives-ouvertes.fr/inria-00450935

]. S. Khan, E. Casseau, and &. D. Ménard, High speed reconfigurable SWP operator for multimedia processing using redundant data representation, Information Sciences and Computer Engineering, vol.1, pp.45-52, 2010.
DOI : 10.1109/asap.2009.13

URL : https://hal.archives-ouvertes.fr/inria-00480330

D. Ménard, R. Rocher, and &. O. Sentieys, Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, issue.10, pp.3197-3208, 2008.
DOI : 10.1109/TCSI.2008.923279

]. D. Ménard-08b, R. Ménard, R. Serizel, &. O. Rocher, and . Sentieys, Accuracy Constraint Determination in Fixed-Point System Design, EURASIP Journal on Embedded Systems, vol.67, issue.5, pp.12-12, 2008.
DOI : 10.1109/93.388209

D. Ménard, D. Chillet, and &. O. Sentieys, Floating-to-Fixed-Point Conversion for Digital Signal Processors, EURASIP Journal on Applied Signal Processing, vol.37, issue.8, pp.1-19, 2006.
DOI : 10.1155/ASP/2006/96421

]. R. Rocher-06b, D. Rocher, N. Ménard, &. O. Hervé, and . Sentieys, Fixed-Point Configurable Hardware Components, EURASIP Journal on Embedded Systems, vol.35, issue.23, pp.1-13, 2006.
DOI : 10.1155/ES/2006/23197

J. C. Naud, D. Ménard, G. Caffarena, O. Sentieys, T. Saidi et al., A Discrete Model for Correlation Between Quantization Noises. Minor revision after submission in IEEE Transactions on Circuits and Systems II Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe, Technique et Science Informatiques, vol.22, issue.6, pp.783-810, 2003.
URL : https://hal.archives-ouvertes.fr/hal-00743413

]. J. Naud-11c, D. Naud, O. Ménard, H. N. Sentieys-ménard, F. Nguyen et al., Évaluation de la précision en virgule fixe dans le cas des structures conditionnelles Soumis à Technique et Science Informatiques Exploiting Reconfigurable SWP Operators for Multimedia Applications, Conférences internationales Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.11-51, 2011.

A. Banciu, E. Casseau, D. Ménard, and &. T. Michel, Stochastic modeling for floating-point to fixed-point conversion, 2011 IEEE Workshop on Signal Processing Systems (SiPS), pp.46-50, 2011.
DOI : 10.1109/SiPS.2011.6088971

URL : https://hal.archives-ouvertes.fr/hal-00746791

D. Nguyen, &. O. Ménard, and . Sentieys, Novel Algorithms for Word-length Optimization, Proc. European Signal Processing Conference (EUSIPCO), pp.11-54, 2011.

]. M. Alam-11b, O. Alam, D. Berder, &. O. Ménard, and . Sentieys, Accurate Energy Consumption Evaluation of Preamble Sampling MAC Protocols for WS, Proc. Architecture of Computing Systems (ARCS), p.71, 2011.

]. J. Naud-11b, Q. Naud, D. Meunier, &. O. Ménard, and . Sentieys, Fixed-point Accuracy Evaluation in the Context of Conditional Structures, Proc. European Signal Processing Conference (EUSIPCO), p.22, 2011.

]. K. Parashar-10a, D. Parashar, R. Ménard, &. O. Rocher, and . Sentieys, Estimating Frequency Characteristics of Quantization Noise for Performance Evaluation of Fixed Point Systems, Proc. European Signal Processing Conference (EUSIPCO), pp.552-556, 2010.

]. K. Parashar-10b, D. Parashar, R. Ménard, O. Rocher, D. Sentieys et al., Fast performance evaluation of fixed-point systems with un-smooth operators, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.2010-2016
DOI : 10.1109/ICCAD.2010.5654064

]. K. Parashar-10c, R. Parashar, D. Rocher, &. O. Ménard, and . Sentieys, A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems, 2010 23rd International Conference on VLSI Design, pp.11-65, 2010.
DOI : 10.1109/VLSI.Design.2010.66

]. K. Parashar-10d, R. Parashar, D. Rocher, &. O. Ménard, and . Sentieys, Analytical approach for analyzing quantization noise effects on decision operators, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, pp.1554-1557, 2010.
DOI : 10.1109/ICASSP.2010.5495520

D. Parashar-10e-]-karthick-parashar, R. Ménard, &. Rocher, and . Olivier-sentieys, Shaping Probability Density Function of Quantization Noise in Fixed Point Systems, Proc. Annual Asilomar Conference on Signals, Systems, and Computers, pp.2010-2023

A. Banciu, E. Casseau, D. Ménard, and &. T. Michel, A case study of the stochastic modeling approach for range estimation, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.301-308, 2010.
DOI : 10.1109/DASIP.2010.5706256

URL : https://hal.archives-ouvertes.fr/inria-00554268

D. Ménard, D. Novo, R. Rocher, F. Catthoor, and &. O. Sentieys, Quantization Mode Opportunities in Fixed-Point System Design, Proc. European Signal Processing Conference (EUSIPCO), pp.542-546, 2010.

H. Nguyen, D. Ménard, and &. O. Sentieys, Dynamic precision scaling for low power WCDMA receiver, 2009 IEEE International Symposium on Circuits and Systems, pp.14-75, 2009.
DOI : 10.1109/ISCAS.2009.5117721

URL : https://hal.archives-ouvertes.fr/inria-00432584

D. Nguyen, &. O. Ménard, and . Sentieys, Design of Optimized Fixed-point WCDMA Receiver, Proc. European Signal Processing Conference (EUSIPCO), pp.14-75, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00432581

]. S. Khan-09a, E. Khan, &. D. Casseau, and . Ménard, Reconfigurable SWP Operator for Multimedia Processing, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, pp.199-202, 2009.
DOI : 10.1109/ASAP.2009.13

D. Ménard, E. Casseau, S. Khan, O. Sentieys, S. Chevobbe et al., Reconfigurable Operator Based Multimedia Embedded Processor, Proc. International Workshop on Applied Reconfigurable Computing (ARC), pp.39-49, 2009.
DOI : 10.1109/79.826409

]. S. Khan-09b, E. Khan, &. D. Casseau, and . Ménard, SWP for multimedia operator design, Proc. Conference, Sciences of Electronic, Technologies of Information and Telecommunications, pp.14-75, 2009.

T. Hilaire, D. Ménard, and &. O. Sentieys, Bit accurate roundoff noise analysis of fixed-point linear controllers, 2008 IEEE International Conference on Computer-Aided Control Systems, pp.607-612, 2008.
DOI : 10.1109/CACSD.2008.4627366

URL : https://hal.archives-ouvertes.fr/inria-00459266

D. Nguyen, R. Ménard, &. O. Rocher, and . Sentieys, Energy reduction in wireless system by dynamic adaptation of the ?xed-point speci ?cation, Proc. Workshop on Design and Architectures for Signal and Image Processing (DASIP), pp.14-75, 2008.

N. Hervé, D. Ménard, and &. O. Sentieys, About the Imporance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations, Proc. International Workshop on Applied Reconfigurable Computing (ARC), Rio de Janeiro, pp.11-57, 2007.

T. Hilaire, D. Ménard, and &. O. Sentieys, Roundoff noise of finite wordlength realizations with the implicit state-space framework, Proc. European Signal Processing Conference (EUSIPCO), pp.14-74, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00459286

D. Ménard, R. Rocher, O. Sentieys, and &. R. Serizel, Noise model for Accuracy Constraint Determination in Fixed-point Systems, Proc. Workshop on Design and Architectures for Signal and Image Processing (DASIP), grenoble, pp.12-36, 2007.

]. R. Rocher-07a, D. Rocher, P. Ménard, &. O. Scalart, and . Sentieys, Analytical accuracy evaluation of Fixed-Point Systems, Proc. European Signal Processing Conference (EUSIPCO), pp.12-26, 2007.

]. R. Rocher-06a, N. Rocher, D. Herve, &. O. Ménard, and . Sentieys, Fixed-point Configurable Hardware Components for Adaptive Filters, 2006 IEEE International Symposium on Circuits and Systems, pp.14-74, 2006.
DOI : 10.1109/ISCAS.2006.1693331

R. Rocher, D. Ménard, P. Scalart, and &. O. Sentieys, Accuracy Evaluation of Fixed-Point APA algorithm, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., pp.57-60, 2005.
DOI : 10.1109/ICASSP.2005.1416239

URL : https://hal.archives-ouvertes.fr/inria-00482702

N. Herve, D. Ménard, and &. O. Sentieys, Data wordlength optimization for FPGA synthesis, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., pp.623-628, 2005.
DOI : 10.1109/SIPS.2005.1579941

URL : https://hal.archives-ouvertes.fr/inria-00482912

F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer et al., Co-Design of Massively Parallel Embedded Processor Architectures, Proc. Workshop on Reconfigurable Communication-Centric SoCs, p.51, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00083717

R. Rocher, D. Ménard, P. Scalart, and &. O. Sentieys, Accuracy Evaluation of Fixed-point LMS algorithm, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.237-240, 2004.
URL : https://hal.archives-ouvertes.fr/inria-00482940

]. D. Ménard-04a, R. Ménard, P. Rocher, &. O. Scalart, and . Sentieys, SQNR determination in non-linear and nonrecursive fixed-point systems, Proc. European Signal Processing Conference (EUSIPCO), pp.1349-1352, 2004.

]. D. Ménard-03c, M. Ménard, S. Guitton, &. O. Pillement, and . Sentieys, Design and Implementation of WCDMA Platforms : Challenges and Trade-offs, Proc. International Signal Processing Conference, pp.14-72, 2003.

D. Ménard, D. Chillet, F. Charot, and &. O. Sentieys, Automatic floating-point to fixed-point conversion for DSP code generation, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '02, pp.270-276, 2002.
DOI : 10.1145/581630.581674

]. D. Ménard-02c, P. Ménard, &. O. Quemerais, and . Sentieys, Influence of fixed-point DSP architecture on computation accuracy, Proc. European Signal Processing Conference (EUSIPCO), pp.587-590, 2002.

]. D. Ménard-02e, &. O. Ménard, and . Sentieys, A methodology for evaluating the precision of fixed-point systems, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2002.

]. D. Ménard-02f, &. O. Ménard, and . Sentieys, Automatic evaluation of the accuracy of fixed-point algorithms, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, p.22, 2002.
DOI : 10.1109/DATE.2002.998351

C. C. Naud-11a-]-j, D. Naud, Q. Ménard, &. O. Meunie, and . Sentieys, Evaluation de la précision en virgule fixe dans le cas des structures conditionnelles, Proc. Symposium en Architectures nouvelles de machines (SYMPA), Saint Malo, pp.22-29, 2011.

]. R. Rocher-07b, D. Rocher, O. Ménard, &. P. Sentieys, and . Scalart, Evaluation de la précision des systèmes en Virgule Fixe, Proc. Colloque sur le traitement du signal et des images (GRETSI), p.22, 2007.

]. N. Hervé-05a, D. Hervé, &. O. Ménard, and . Sentieys, Synthèse d'architecture sur FPGA sous contrainte de précision des calculs, Proc. Symposium en Architectures nouvelles de machines (SYMPA), Le Croisic, p.57, 2005.

]. N. Hervé-05b, D. Hervé, &. O. Ménard, and . Sentieys, Optimisation de la largeur des opérateurs arithmétiques en synthèse de haut-niveau, Proc. Colloque sur le traitement du signal et des images (GRETSI), p.57, 2005.

R. Rocher, D. Ménard, O. Sentieys, and &. P. Scalart, Evaluation de la précision des Algorithmes de Projection Affine en Virgule Fixe Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe, Proc. Colloque sur le traitement du signal et des images (GRETSI) Proc. Symposium en Architectures nouvelles de machines (SYMPA), p.22, 2002.

D. Ménard and O. Sentieys, Influence du modèle de l'architecture des DSPs virgule fixe sur la précision des calculs, Proc. Colloque sur le traitement du signal et des images (GRETSI), 2001.

]. D. Ménard-03b, M. Ménard, R. Guitton, S. David, &. O. Pillement et al., Évaluation comparative de platesformes reconfigurables et programmables pour les télécommunications de 3ème génération, Proc

G. Alefeld and J. Herzberger, Introduction to Interval Computations, pp.22-46, 1983.

A. Device, TigerSHARC Hardware Specification. Analog Device, december 1999, p.52

S. Balacoo, C. Rommel, and J. Weiner, Searching for the Total Size of the Embedded Software Engineering Market, february 2011, p.15

C. Barnes, B. N. Tran, and S. Leung, On the statistics of fixed-point roundoff error, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.33, issue.3, pp.595-606, 1985.
DOI : 10.1109/TASSP.1985.1164611

F. Berens and N. Naser, Algorithm to System-on-Chip Design Flow that Leverages System Studio and SystemC 2.0.1. Synopsys Inc., march, p.23, 2004.

J. Bier, BDTI Certified Benchmark Results, p.17, 2010.

J. Bier, Jeff Bier's Impulse Response-The Floating-Point Future, october 2010, p.18

M. Blair, S. Obenski, and P. Bridickas, Patriot Missile Defense : Software Problem Led to System Failure at Dhahran, Saudi Arabia, p.16, 1992.

S. Blinnikov and R. Moessner, Expansions for nearly Gaussian distributions. Astronomy and astrophysics suplement series, pp.193-205, 1998.

G. Caffarena, J. A. López, C. Fernandez, and . Carreras, SQNR Estimation of Fixed-Point DSP Algorithms, EURASIP Journal on Advances in Signal Processing, vol.2010, issue.1, pp.24-31, 2010.
DOI : 10.1109/TCSI.2004.823652

G. Caffarena, J. A. López, G. Leyva, C. Carreras, and O. Nieto-taladriz, Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs, International Journal of Reconfigurable Computing, vol.8, issue.3, pp.60-61, 2009.
DOI : 10.1109/82.868453

M. Cantin, Y. Savaria, D. Prodanos, and P. Lavoie, An automatic word length determination method, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), pp.53-56, 2001.
DOI : 10.1109/ISCAS.2001.921982

M. Cantin, Y. Savaria, D. Prodanos, and P. Lavoie, A Metric for Automatic Word-Length Determination of Hardware Datapaths, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.10, pp.2228-2231, 2006.
DOI : 10.1109/TCAD.2005.862733

C. Caraiscos and B. Liu, A roundoff error analysis of the LMS adaptive algorithm, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.32, issue.1, pp.34-41, 1984.
DOI : 10.1109/TASSP.1984.1164286

J. Chesneaux, L. Didier, and F. Rico, Fixed CADNA library, Proc. conference on Real Number Conference (RNC), pp.215-221, 2003.

M. Clark, M. Mulligan, D. Jackson, and D. Linebarger, Accelerating Fixed-Point Design for MB-OFDM UWB Systems, CommsDesign, p.18, 2005.

G. Constantinides, P. Cheung, and W. Luk, Truncation noise in fixed-point SFGs, Electronics Letters, vol.35, issue.23, pp.2012-2014, 1999.
DOI : 10.1049/el:19991375

G. Constantinides, P. Cheung, and W. Luk, Roundoff-noise shaping in filter design, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), pp.57-60, 2000.
DOI : 10.1109/ISCAS.2000.858687

G. A. Constantinides, Word-length optimization for differentiable nonlinear systems, ACM Transactions on Design Automation of Electronic Systems, vol.11, issue.1, pp.26-43, 2006.
DOI : 10.1145/1124713.1124716

M. Coors, H. Keding, O. Luthje, and H. Meyr, Integer code generation for the TI TMS320C62X, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), p.23, 2001.
DOI : 10.1109/ICASSP.2001.941121

L. D. Coster and . Ku-leuven, Bit-True Simulation of Digital Signal Processing Applications, p.23, 1999.

L. De-coster, M. Ade, R. Lauwereins, and J. A. Peperstraete, Code generation for compiled bit-true simulation of DSP applications, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210), pp.9-14, 1998.
DOI : 10.1109/ISSS.1998.730590

. Coware, CoWare Signal Processing Designer, Implementing DSP Algorithms for Complex Wireless System Design, pp.17-23, 2009.

M. Daumas and G. Melquiond, Certification of bounds on expressions involving rounded operators, ACM Transactions on Mathematical Software, vol.37, issue.1, pp.1-20, 2010.
DOI : 10.1145/1644001.1644003

URL : https://hal.archives-ouvertes.fr/hal-00127769

F. De-dinechin, C. Klein, and B. Pasca, Generating high-performance custom floating-point pipelines, 2009 International Conference on Field Programmable Logic and Applications, pp.59-64, 2009.
DOI : 10.1109/FPL.2009.5272553

URL : https://hal.archives-ouvertes.fr/ensl-00379154

L. H. De-figueiredo and J. Stolfi, Affine Arithmetic: Concepts and Applications, Numerical Algorithms, vol.37, issue.1-4, pp.147-158, 2004.
DOI : 10.1023/B:NUMA.0000049462.70970.b6

D. Delmas, E. Goubault, S. Putot, J. Souyris, K. Tekkal et al., Towards an industrial use of FLUC- TUAT on safety-critical avionics software, Proc. International Workshop on Formal Methods for Industrial Critical Systems (FMICS), pp.53-69, 2009.

M. Dillinger, K. Madani, and N. Alonistioti, Software Defined Radio : Architectures, Systems and Functions, p.92, 2003.

B. Evans, Modem Design, Implementation, and Testing Using NI's LabVIEW, National Instrument Academic Day, p.17, 2005.

J. Eyre and J. Bier, DSPs court the consumer, IEEE Spectrum, vol.36, issue.3, pp.47-53, 1999.
DOI : 10.1109/6.750400

J. Eyre and J. Bier, The evolution of DSP processors, IEEE Signal Processing Magazine, vol.17, issue.2, pp.43-51, 2000.
DOI : 10.1109/79.826411

T. Feo and M. Resende, A probabilistic heuristic for a computationally difficult set covering problem, Operations Research Letters, vol.8, issue.2, pp.67-71, 1989.
DOI : 10.1016/0167-6377(89)90002-3

M. Fingerroff, High-Level Synthesis Blue Book. Xlibris, p.17, 2010.

P. D. Fiore, Efficient Approximate Wordlength Optimization, IEEE Transactions on Computers, vol.57, issue.11, pp.1561-1570, 2008.
DOI : 10.1109/TC.2008.87

L. Fousse, G. Hanrot, V. Lefèvre, P. Pélissier, and P. Zimmermann, MPFR, ACM Transactions on Mathematical Software, vol.33, issue.2, p.23, 2007.
DOI : 10.1145/1236463.1236468

URL : https://hal.archives-ouvertes.fr/inria-00070266

J. Fridman, Sub-word parallelism in digital signal processing, IEEE Signal Processing Magazine, vol.17, issue.2, pp.27-35, 2000.
DOI : 10.1109/79.826409

K. Han, Automating transformations from floating-point to fixed-point for implementing digital signal processing algorithms, p.55, 2006.

K. Han and B. Evans, Wordlength optimization with complexity-and-distortion measure and its application to broadband wireless demodulator design, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.37-40

B. Hassibi and H. Vikalo, On the sphere-decoding algorithm I. Expected complexity, IEEE Transactions on Signal Processing, vol.53, issue.8, pp.2806-2818, 2005.
DOI : 10.1109/TSP.2005.850352

N. Hervé, Contributions à la synthèse d'architecture virgule fixe à largeurs multiples, pp.5-71, 2007.

T. Hilaire, Analyse et synthèse de l'implémentation de lois de contrôle-commande en précision finie. Phd, p.74, 2006.

T. Hilaire, Finite Wordlength Realizations Toolbox User's Guide, p.74, 2009.

T. Hill, AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs. White papers, Xilinx, p.18, 2006.

A. Joshi, Embedded Systems : Technologies and Markets, VDC Research, p.15, 2009.

J. Kang and W. Sung, Fixed-Point C Compiler for TMS320C50 Digital Signal Processor, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), p.23, 1997.

H. Keding, Pain Killers for the Fixed-Point Design Flow, pp.17-23, 2010.

S. Khan, Development of high performance hardware architectures for multimedia applications. Phd, Université Rennes 1, Lannion, september 2010, pp.75-81
URL : https://hal.archives-ouvertes.fr/tel-00554668

S. Kim, K. Kum, and S. Wonyong, Fixed-Point Optimization Utility for C and C++ Based Digital Signal Processing Programs, IEEE Transactions on Circuits and Systems II -Analog and Digital Signal Processing, pp.1455-1464, 1998.

S. Kim and W. Sung, A Floating-point to Fixed-point Assembly program Translator for the TMS 320C25, IEEE Transactions on Circuits and Systems, vol.41, issue.11, pp.730-739, 1994.

S. Krithivasan, M. J. Schulte, and J. Glossner, A Subword-Parallel Multiplication and Sum-of-Squares Unit, Proc. IEEE Computer Society Annual Symposium on VLSI, pp.273-82, 2004.

K. Kum, J. Y. Kang, and W. Y. Sung, AUTOSCALER for C : An optimizing floating-point to integer C program converter for fixed-point digital signal processors, IEEE Transactions on Circuits and Systems II -Analog and Digital Signal Processing, pp.840-848, 2000.

M. Lau, K. Ling, and Y. Chu, Energy-aware probabilistic multiplier, Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, CASES '09, pp.281-290, 2009.
DOI : 10.1145/1629395.1629434

M. Loève, Probability Theory, pp.10-47, 1977.

T. Lukasiak, Extended-Precision Fixed-Point Arithmetic on the Blackfin Processor Platform, p.90, 2003.

J. A. López, G. Caffarena, C. Carreras, and O. Nieto-taladriz, Fast and accurate computation of the round-off noise of linear time-invariant systems, IET Circuits, Devices & Systems, vol.2, issue.4, pp.393-408, 2008.
DOI : 10.1049/iet-cds:20070198

A. Maheshwari, W. Burleson, and R. Tessier, Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.299-311, 2004.
DOI : 10.1109/TVLSI.2004.824302

. Mathworks, Fixed-Point Blockset User's Guide (ver. 2.0), pp.17-23, 2001.

M. Graphics, Algorithmic C Data Types. Mentor Graphics, version 1.3 edition, p.23, 2008.

H. N. Nguyen, Optimisation de la précision de calcul pour la réduction d'énergie des systèmes embarqués Rennes I, A soutenir 16 décembre 2011, pp.51-75

D. Novo, B. Bougard, and A. , Lambrechts andL. Van der Perre, and F. Catthoor. Scenario-based fixed-point data format refinement to enable energy-scalable software defined radios, Proc. IEEE/ACM conference on Design, Automation and Test in Europe (DATE), pp.722-727, 2008.

A. Oppenheim and R. W. Schafer, Discrete Time Signal Processing. Prentice All Signal Processing series, pp.24-30, 1999.

O. Sentieys, J. P. Diguet, and J. L. Philippe, GAUT : a High Level Synthesis Tool dedicated to real time signal processing application, IEEE/ACM European Design Automation Conference, p.59, 1995.

E. Ozer, A. P. Nisbet, and D. Gregg, Stochastic Bitwidth Approximation Using Extreme Value Theory for Customizable Processors, p.49, 2003.

P. R. Panda, B. V. Silpa, A. Shrivastava, and K. Gummidipudi, Power-efficient System Design, p.16, 2010.
DOI : 10.1007/978-1-4419-6388-8

B. Parhami, Gaining Speed and Cost Advantage from Imprecise Computer Arithmetic, Seminar of Berkeley Initiative in Soft Computing, p.90, 2000.

R. Rocher, Évaluation analytique de la précision des systèmes en virgule fixe. Phd, Université Rennes 1, pp.28-34, 2006.

S. Roy and P. Banerjee, An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design, IEEE Transactions on Computers, vol.54, issue.7, pp.886-896, 2005.
DOI : 10.1109/TC.2005.106

G. Rubino and B. Tuffin, Rare Event Simulation using Monte Carlo Methods, p.90, 2009.
DOI : 10.1002/9780470745403

URL : https://hal.archives-ouvertes.fr/hal-00787654

T. Saidi, Hardware Architectures for WCDMA technology extended to mulitple-antenna systems. Phd, p.72, 2008.
URL : https://hal.archives-ouvertes.fr/tel-00446060

R. Serizel, Implantation en virgule fixe d'un codeur audio, p.36, 2006.

C. Shi and R. Brodersen, A perturbation theory on statistical quantization effects in fixed-point DSP with nonstationary inputs, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.373-376, 2004.

A. Sripad and D. L. Snyder, A necessary and sufficient condition for quantization errors to be uniform and white, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.25, issue.5, pp.442-448, 1977.
DOI : 10.1109/TASSP.1977.1162977

W. Strauss, DSP chips take on many forms. DSP-FPGA.com Magazine, p.17, 2006.

A. Tisserand, Function approximation based on estimated arithmetic operators, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers, pp.1798-1802, 2009.
DOI : 10.1109/ACSSC.2009.5470208

URL : https://hal.archives-ouvertes.fr/inria-00446527

S. Wadekar and A. Parker, Accuracy sensitive word-length selection for algorithm optimization, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), pp.54-61, 1998.
DOI : 10.1109/ICCD.1998.727023

B. Widrow, Statistical Analysis of Amplitude Quantized Sampled-Data Systems. Transaction on AIEE, Part. II : Applications and Industry, pp.555-568, 1960.

B. Widrow and I. Kollár, Quantization Noise : Roundoff Error in Digital Computation, Signal Processing, Control, and Communications, pp.24-27, 2008.
DOI : 10.1017/CBO9780511754661

P. W. Wolniansky, G. J. Foschini, G. D. Golden, and R. A. Valenzuela, V-BLAST: an architecture for realizing very high data rates over the rich-scattering wireless channel, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), p.41, 2008.
DOI : 10.1109/ISSSE.1998.738086

B. Wu, J. Zhu, and F. Najm, An analytical approach for dynamic range estimation, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.472-477, 2004.
DOI : 10.1145/996566.996699

S. Yoshizawa and Y. Miyanaga, Tunable word length architecture for low power wireless OFDM demodulator, 2006 IEEE International Symposium on Circuits and Systems, pp.2789-2792, 2006.
DOI : 10.1109/ISCAS.2006.1693203

R. Du, b) Évolution de la puissance du signal P sout , du bruit du récepteur P nout et de la contrainte de précision P b en fonction, p.78