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Design of SRAM for CMOS 32nm

Abstract : The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.
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Submitted on : Monday, July 9, 2012 - 12:02:29 PM
Last modification on : Monday, September 13, 2021 - 2:44:02 PM
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  • HAL Id : tel-00715803, version 1


Lahcen Hamouche. Design of SRAM for CMOS 32nm. Other. INSA de Lyon, 2011. English. ⟨NNT : 2011ISAL0013⟩. ⟨tel-00715803⟩



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