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Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse : application aux mémoires et fonctions logiques

Abstract : Driven by the strong growth of smartphone and tablet devices, an exponential growth for the mobile SoC market is forecasted up to 2016. These systems, designed in the latest nanometre technology, require very high speeds to deliver tremendous performances, while consuming remarkably little. However, designing such systems at the nanometre scale introduces many challenges due to the emphasis of parasitic phenomenon effects driven by the scaling of bulk MOSFETs, making circuits more sensitive to the manufacturing process fluctuations and less energy efficient. Undoped thin-film planar fully depleted silicon-on-insulator (FDSOI) devices are being investigated as an alternative to bulk devices in 28nm node and beyond, thanks to its excellent short-channel electrostatic control, low leakage currents and immunity to random dopant fluctuation. This compelling technology appears to meet the needs of nomadic devices, combining high performance and low power consumption. However, to be useful, it is essential that this technology is compatible with low operating power design platforms. A major challenge for this technology is to provide various device threshold voltages (VT), trading off power consumption and speed. The research work presented in this thesis has contributed to the development of a multi-VT design platform in FDSOI planar technology on thin buried oxide (UTB) for the 28nm and below technology nodes. In this framework, the key elements of the low power design platform in bulk planar technology have been studied. Based on this analysis, different architectures of FDSOI multi-VT MOSFETs have been developed. The analysis on the layout of elementary circuits, such as standard cells and SRAM cells, has put forward two reliable, efficient and low technological complexity multi- strategies. Finally, the performances of these solutions have been evaluated on a critical path extracted from the ARM Cortex A9 processor and a high-density 6T SRAM cell (0.120µm²). Also, an SRAM cell with four transistors has been proposed, highlighting the design flexibility brought by these solutions. This thesis has resulted in many publications, communications and patents. Today, the majority of the results obtained have been transferred to STMicroelectronics, where the industrialization is in progress.
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Submitted on : Wednesday, December 19, 2012 - 6:01:58 PM
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Jean-Philippe Noel Noël. Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse : application aux mémoires et fonctions logiques. Autre. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT069⟩. ⟨tel-00701765v2⟩



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