P. Chaque, . Représente-un-historique, and . Donc-une-trace, La fusion de S 1 et S 2 génère donc un état S merge dont le PC est défini par : PC merge = PC 1 ? PC 2 = (a 1 > 0 ? a 2 > 1) ? (a 1 > 20 ? a 2 > 10) Cette expression mathématique implique que la fusion

E. Effet, ? (a 1 > 20 ? a 2 > 10) représente aussi d'autres historiques d'exécution : ? (a 1 > 0 ? a 2 > 10)

E. Effet, expression (a 1 > 0 ? a 1 > 20) ? (a 2 > 1 ? a 2 > 10) définit un sur-ensemble contenant les traces faisables représentées par

. Ainsi, des comportements infaisables sont susceptibles d'apparaitre (les comportement engendrés par les historiques d'exécution qu'a introduit la disjonction de (a 1 > 0? a 2 > 10) et de (a 1 > 20? a 2 > 1)) Ce qui nuit considérablement à la précision des temps calculés. C'est pourquoi, la disjonction que nous utilisons n'est pas le simple opérateur mathématique, mais plutôt une disjonction entre PCs. Autrement dit, chaque PC est considéré comme une entité indivisible par l'opérateur de disjonction. Ainsi, durant notre analyse le PC merge est sauvegardé comme suit

B. La-figure-5 and C. , Les deux traces à gauche (A,B) sont générées durant l'exécution symbolique de la fonction acquisition La trace (C), en gris, est la trace obtenue après la fusion des deux précédentes traces. Durant l'exécution symbolique plusieurs traces convergent vers un état fortement similaire, Cet état est caractérisé par : ? (1) C'est un point de l'exécution qui rassemble plusieurs traces qui ont des historiques d'exécution différents

. Dans-la-figure-5, ) un fetcher (F) qui contient les instructions de 10 à 15) une unité de Branchement (BPU) qui contient l'instruction 8, (4) une unité de lecture et d'écriture mémoire (LSU) qui exécute l'instruction 6, (5) une unité d'achèvement qui stocke les résultats des exécutions des instructions 4 and 5, ) un dispatcher (D) qui dispatche les instructions 7 et 9) une mémoire cache d'instructions (IC) qui contient les instructions de 1 à 15

. Lorsque, nous identifions des états fortement similaires nous les fusionnons. Cette fusion n'a aucun impact sur les temps d'exécution calculés à posteriori

A. , R. Mueller, F. Whalley, D. , A. Harmon et al., Bounding worst-case instruction cache performance, IEEE Real-Time Systems Symposium, pp.172-181, 1994.

B. , B. And-monsuez, and B. , Computing worst case execution time (wcet) by symbolically executing a time-accurate hardware model. IMECS 2009 . The International Multi- Conference of Engineers and Computer Scientists , Special Session : Design, Analysis and Tools for Integrated Circuits and Systems, 2009.

B. , B. And-monsuez, and B. , Computing worst case execution time (wcet) by symbolically executing a time-accurate hardware model (extented version), International Journal of Design Analysis and Tools for Circuits and Systems, vol.1, issue.1, 2009.

B. , B. Monsuez, B. And-védrine, and F. , Computing wcet using symbolic execution . Second International Workshop on Verification and Evaluation of Computer and Communication Systems, 2008.

B. , G. Colin, A. And-petters, and S. , pwcet : A tool for probabilistic worst-case execution time analysis of real-time systems, 2003.

B. , G. Colin, A. And-petters, and S. M. , Wcet analysis of probabilistic hard real-time systems, Proceedings of the 23rd Real-Time Systems Symposium RTSS 2002, pp.279-288, 2002.

B. , J. Fahringer, T. And-scholz, and B. , Symbolic cache analysis for real-time systems, Real-Time Systems, vol.18, pp.181-215, 1999.

B. , E. And-stärk, and R. , Abstract state machines. a method for high-level system design and analysis, 2003.

B. , C. And-rochange, and C. , History-based schemes and implicit path enumeration Workshop on Worst-Case Execution Time (WCET) Analysis (Dagstuhl, 6th Intl Internationales Begegnungs-und Forschungszentrum fur Informatik (IBFI), Schloss Dagstuhl, 2006.

C. , H. And-sainrat, and P. , Otawa, a framework for experimenting wcet computations, p.6, 2006.

C. Ferdinand, R. H. And-wilhelm, and R. , Analyzing the Worst-Case Execution Time by Abstract Interpretation of Executable Code, Automotive Software ? Connected Services in Mobile Networks, pp.1-14, 2006.
DOI : 10.1007/11823063_1

C. , A. Denaro, G. Ghezzi, C. And-pezzé, and M. , Using symbolic execution for verifying safety-critical systems, ESEC/FSE-9 : Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering, pp.142-151, 2001.

C. , A. And-puaut, and I. , A modular and retargetable framework for tree-based wcet analysis, Proc. of the 13th Euromicro Conference on Real-Time Systems, pp.37-44, 2001.

C. , M. Brega, R. And-gross, and T. , Approximation of worst-case execution time for preemptive multitasking systems, LCTES '00 : Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pp.178-198, 2001.

C. , P. And-cousot, and R. , Abstract interpretation : a unified lattice model for static analysis of programs by construction or approximation of fixpoints, Conference Record of the Fourth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp.238-252, 1977.

E. , J. Ermedahl, A. Sjödin, M. Gustavsson, J. And-hansson et al., Towards industry strength worst-case execution time analysis, 1999.

E. , J. Ermedahl, A. And-stappert, and F. , Validating a worst-case execution time analysis method for an embedded processor, Tech. Rep, 2001.

E. , J. And-jonsson, and B. , Processor pipelines and their properties for static wcet analysis, Proceedings of EMSOFT 02 : Second International Conference on Embedded Software, pp.334-348, 2002.

E. , A. And-gustafsson, and J. , Deriving annotations for tight calculation of execution time, Euro-Par '97 : Proceedings of the Third International Euro-Par Conference on Parallel Processing, pp.1298-1307, 1997.

F. , C. Kastner, D. Langenbach, M. Martin, F. Schmidt et al., Run-time guarantees for real-time systems ? the USES approach, GI Jahrestagung, pp.410-419, 1999.

F. , C. And-wilhelm, and R. , On predicting data cache behavior for real-time systems, LCTES '98 : Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pp.16-30, 1998.

H. , C. A. Arnold, R. D. Mueller, F. Harmon, M. G. And-walley et al., Bounding pipeline and instruction cache performance, IEEE Trans. Comput, vol.48, pp.1-53, 1999.

H. , S. Reps, T. And-binkley, and D. , Interprocedural slicing using dependence graphs, PLDI '88 : Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, pp.35-46, 1988.

I. Bate, P. Conmy, and T. K. , Use of Modern Processors in Safety-Critical Applications, The Computer Journal, vol.44, issue.6, pp.531-543, 2001.
DOI : 10.1093/comjnl/44.6.531

J. Souyris, E. Le-pavec, G. H. And-heckmann, and R. , Computing the worst case execution time of an avionics program by abstract interpretation

L. , X. Roychoudhury, A. And-mitra, and T. , Modeling out-of-order processors for wcet analysis . Real-Time Syst, pp.195-227, 2006.

L. , Y. S. Malik, S. And-wolfe, and A. , Efficient microarchitecture modeling and path analysis for real-time software, RTSS '95 : Proceedings of the 16th IEEE Real-Time Systems Symposium, p.298, 1995.

L. , S. Bae, Y. H. Jang, G. T. Rhee, B. Min et al., An accurate worst case timing analysis for risc processors, IEEE Trans. Softw. Eng, vol.21, pp.7-593, 1995.

L. , M. Hansson, H. And-thane, and H. , Using measurements to derive the worst-case execution time, RTCSA '00 : Proceedings of the Seventh International Conference on Real-Time Systems and Applications, p.15, 2000.

L. , C. L. And-layland, and J. W. , Scheduling algorithms for multiprogramming in a hard-realtime environment, J. ACM, vol.20, issue.1, pp.46-61, 1973.

L. , T. And-stenström, and P. , Integrating path and timing analysis using instruction-level simulation techniques, LCTES '98 : Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pp.1-15, 1998.

L. , T. And-stenström, and P. , An integrated path and timing analysis method based on cycle-level symbolic execution. Real-Time Syst, pp.2-3, 1999.

L. , T. And-stenström, and P. , A method to improve the estimated worst-case performance of data caching, RTCSA '99 : Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications, p.255, 1999.

L. , T. And-stenström, and P. , Timing anomalies in dynamically scheduled microprocessors, RTSS '99 : Proceedings of the 20th IEEE Real-Time Systems Symposium, p.12, 1999.

M. , L. And-rival, and X. , Trace partitioning in abstract interpretation based static analyzers, European Symposium on Programming (ESOP'05), pp.5-20, 2005.

M. , B. And-védrine, and F. , Modélisation d'une plate-forme multi-processeurs pour calculer et contraindre des temps d'exécution, Contrat ANR Applications Parallèles pour l'Embarqué, 2007.

O. , G. And-sjodin, and M. , Worst case execution time analysis for modern hardware architectures, Proc. of ACM SIGPLAN, Workshop on Languages, Compilers and Tools for Real-Time Systems, pp.47-55, 1997.

P. , C. Y. , A. Shaw, and A. C. , Experiments with a program timing tool based on source-level timing schema, Computer, vol.24, issue.5, pp.48-57, 1991.

P. Lokuciejewski, H. Falk, and M. S. , Influence of procedure cloning on WCET prediction, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.137-142, 2007.
DOI : 10.1145/1289816.1289852

P. , C. S. And, and W. Visser, A survey of new trends in symbolic execution for software testing and analysis, Int. J. Softw. Tools Technol. Transf, vol.11, issue.4, pp.339-353, 2009.

P. , P. And, and A. Burns, A review of worst-case execution-time analysis, Journal of Real-Time Systems, vol.18, issue.23, pp.115-128, 2000.

P. , P. And-koza, and C. , Calculating the maximum, execution time of real-time programs. Real-Time Syst, pp.159-176, 1989.

P. , P. P. And-schedl, and A. , Computing maximum task execution times ? a graphbasedapproach . Real-Time Syst, pp.67-91, 1997.

R. Heckmann and C. F. , Worst case execution time prediction by static program analysis, Parallel and Distributed Processing Symposium. Proceedings. 18th International Volume, pp.125-134, 2004.

R. , J. Hoffmann, D. Gerlach, J. Kropf, T. Rosenstiehl et al., The simulation semantics of systemc, DATE '01 : Proceedings of the conference on Design, automation and test in Europe, pp.64-70, 2001.

S. , F. And-gustafsson, and J. , Determining the worst case instruction cache miss-ratio, Proceedings of Workshop On Embedded System Codesign (ESCODES'02, p.2002, 2002.

T. , H. Ferdinand, C. Saarbrucken, A. A. And-wilhelm, and R. , Fast and precise wcet prediction by separated cache and path analyses, Real-Time Systems, vol.18, pp.157-179, 1999.

T. Steven, L. , Y. And-malik, and S. , Performance analysis of embedded software using implicit path enumeration, Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp.456-461, 1995.

T. Steven, L. , Y. And-malik, and S. , Performance analysis of embedded software using implicit path enumeration, Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp.456-461, 1995.

W. , R. T. Healy, C. A. Whalley, D. B. Mueller, F. et al., Timing analysis for data caches and set-associative caches, RTAS '97 : Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97), p.192, 1997.

W. , R. T. Mueller, F. Healy, C. Whalley, D. Harmon et al., Timing analysis for data and wrap-around fill caches, Real-Time Systems, vol.17, pp.209-233, 1999.

W. , R. Engblom, J. Ermedahl, A. Holsti, N. Thesing et al., The worst-case execution-time problem?overview of methods and survey of tools, ACM Trans. Embed. Comput. Syst, vol.7, pp.3-4, 2008.

W. , R. And-wachter, and B. , Abstract interpretation with applications to timing validation, CAV '08 : Proceedings of the 20th international conference on Computer Aided Verification, pp.22-36, 2008.

Z. , N. Burns, A. And, and M. Nicholson, Pipelined processors and worst case execution times. Real-Time Syst, pp.319-343, 1993.