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Analyse des mécanismes mis en jeu lors de l'élaboration par gravure plasma de structures de dimensions déca-nanométriques : Application au transistor CMOS ultime

Abstract : This work focuses on the understanding of the mechanisms involved in plasma etching processes used to design sub-20 nm poly-silicon gates for MOS transistors. The achievement of poly-silicon gates is based on two main steps: lithography followed by plasma etching. Nowadays, the lithographic step limits the scaling down of the silicon gates, since it only leads to a 80 nm resolution using conventional optic lithographies. The current strategy to overcome lithography limitations is to introduce a step of "resist trimming" prior to all the other classical gate etching steps. This particular plasma etching step consists in a controlled lateral erosion of the photoresist patterns elaborated by a classical lithography. In this work, we have deeply studied the resist trimming processes, which are nowadays the only way to get sub-20 nm transistor gates from conventional lithography. Two plasma chemistries HBr/O2 et Cl2/O2 have been investigated. For both chemistries, correlations between lateral etch rates (measured from SEM observations), the chemical surface modifications of the resist patterns (tops and sidewalls) determined by XPS analyses, and the chemical nature of the resist etch-by-products obtained by mass spectrometry have been established. Moreover, controlling this particular step is not the only challenge when achieving sub-20nm transistor gates. A very accurate control and understanding of all the plasma steps (BARC, hard mask open and gate etching) involved in the gate stack processes is also required. It is then important to study the parameters that generate a deviation of the final gate dimension for each of these plasma steps. The aspects that have been investigated are the etching behaviour of the photoresist mask exposed to the plasma, and the chemical nature of the layers that deposit on feature sidewalls and on the reactor walls during the process. This has been done thanks to the development of two experimental procedures based on XPS analyses.
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Submitted on : Thursday, April 5, 2012 - 3:44:29 PM
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Erwine Pargon. Analyse des mécanismes mis en jeu lors de l'élaboration par gravure plasma de structures de dimensions déca-nanométriques : Application au transistor CMOS ultime. Micro et nanotechnologies/Microélectronique. Université de Grenoble, 2004. Français. ⟨tel-00685653⟩

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