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Parallel model checking for multiprocessor architecture

Rodrigo Saad 1
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : In this thesis, we propose and study new algorithms and data structures for model checking nite-state, concurrent systems. We focus on techniques that target shared memory, multi-cores architectures, that are a current trend in computer architectures. In this context, we present new algorithms and data structures for exhaustive parallel model checking that are as effi cient as possible, but also "friendly" with respect to the work-sharing policies that are used for the state space generation (e.g. a work-stealing strategy): at no point do we impose a restriction on the way work is shared among the processors. This includes both the construction of the state space as the detection of cycles in parallel, which is one of the key points of performance for the evaluation of more complex formulas. Alongside the defi nition of enumerative, model checking algorithms for manycores architectures, we also study probabilistic verifi cation algorithms. By the term probabilistic, we mean that, during the exploration of a system, any given reachable state has a high probability of being checked by the algorithm. Probabilistic veri fication trades savings at the level of memory usage for the probability of missing some states. Consequently, it becomes possible to analyze part of the state space of a system when there is not enough memory available to represent the entire state space in an exact manner.
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Submitted on : Monday, March 12, 2012 - 3:31:28 PM
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  • HAL Id : tel-00678352, version 1


Rodrigo Saad. Parallel model checking for multiprocessor architecture. Mathematical Software [cs.MS]. INSA de Toulouse, 2011. English. ⟨tel-00678352⟩



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