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Implémentation matérielle de coprocesseurs haute performance pour la cryptographie asymétrique

Abstract : In this PhD thesis I propose coprocessors architectures for high performance computations of asymmetric primitives like RSA, Elliptic Curves and Pairing. Coprocessors have been implemented in FPGA, and propose the lowest latency ever showed in public litterature on such targets. The novelty of these architectures is the usage of the Residue Number System (RNS), an alternate way to represent big numbers. The work presented here confirms with experimentation the theoretical advantages of this system previously emphasized by [14, 13, 43]. Together with this theoretical advantage RNS computation can be efficiently parallelized, and getting highly regular and parallelized architectures to reach high frequency while computing modular operations in few cycles is possible, whatever is the size of the numbers. For example, a scalar multiplication on a generic 160 elliptic curve can be executed in 0.57 ms on an Altera Stratix, and in 4 ms on a 512 bits curve, compared with classical representations which hardly do the same in twice this time with comparable technologies (except for particular curves). For Pairing the results are even more interesting, since a 4 times division of the latency had been reached by the time [35] was published, and the first time a Pairing over large characteristic fields was executed in less than 1 ms on a FPGA. Eventually, I demonstrate the ability RNS to provide original solutions to protect computations against side channel and perturbation threats. I propose 2 countermeasures to thwart faults and power analysis which can be used on every primitives relying on big number modular arithmetic. These countermeasures are designed to be efficiently adapted on the RNS coprocessors.
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Submitted on : Tuesday, February 28, 2012 - 3:59:38 PM
Last modification on : Thursday, November 15, 2018 - 11:56:34 AM
Document(s) archivé(s) le : Friday, November 23, 2012 - 3:15:18 PM


  • HAL Id : tel-00674975, version 1


Nicolas Guillermin. Implémentation matérielle de coprocesseurs haute performance pour la cryptographie asymétrique. Cryptographie et sécurité [cs.CR]. Université Rennes 1, 2012. Français. ⟨tel-00674975⟩



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