CSS doit fournir un service de contrôle d'intégrité standard (parité ,
? Le chargement des clés et leur identification ? Le stockage des clés ? L'instanciation et l'utilisation des clés ? L'effacement des clés ? La génération de clés A.2.6.2 Réception et identification des clés 1 ,
CSS doit permettre d'effacer de façon sélective les clés rouges ou noires ,
CSS doit accepter les fichiers définissant les interconnexions entre le CSS et les formes d'onde ,
CSS doit pouvoir prendre en compte les alarmes générées par la radio ,
CSS doit effacer la mémoire qui a été utilisée par un objet avant de l'utiliser pour un autre objet ,
« A multi-core AES cryptoprocessor for multi-channel SDR », Military Communiacations and Information Systems Technology Week, 2010. ,
Enseignement ludique de la programmation objets à l'aide des applications de traitement d'image. Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, EDP Sciences, 2011. ,
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios, proceedings of the 7th international symposium on applied reconfigurable computing, 2011. ,
DOI : 10.1007/978-3-642-19475-7_5
URL : https://hal.archives-ouvertes.fr/hal-00668594
A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011. ,
DOI : 10.1109/IPDPS.2011.143
URL : https://hal.archives-ouvertes.fr/hal-00595998
Architectures of flexible symmetric key crypto engines???a survey, ACM Computing Surveys, vol.45, issue.4, 2011. ,
DOI : 10.1145/2501654.2501655
URL : https://hal.archives-ouvertes.fr/hal-00765634
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC, proceedings of the 43rd ACM/IEEE Design Automation Conference, pp.496-501, 2006. ,
An FPGA-based AES-CCM crypto core for IEEE 802, p.11 ,
The Sorcerer's Apprentice Guide to Fault Attacks, Proceedings of the IEEE, vol.94, issue.2, pp.370-382, 2006. ,
DOI : 10.1109/JPROC.2005.862424
Detecting Impersonation Attacks in Future Wireless and Mobile Networks, Secure Mobile Ad-hoc Networks and Sensors, pp.80-95, 2006. ,
Side-channel issues for designing secure hardware implementations, 11th IEEE International On-Line Testing Symposium, pp.118-121, 2005. ,
How to provide a Linux support for dynamic reconfiguration on Xilinx FPGAs, 2008. ,
802.11 denial-of-service attacks: real vulnerabilities and practical solutions, Proceedings of the 12th conference on USENIX Security Symposium, p.2, 2003. ,
API-level attacks on embedded systems, Computer, vol.34, issue.10, pp.67-75, 2001. ,
DOI : 10.1109/2.955101
Generic Design Space Exploration for Reconfigurable Architectures, 19th IEEE International Parallel and Distributed Processing Symposium, pp.163-163, 2005. ,
A scalable hardware architecture to support applications of the haipe 3.1 standard, Military Communications Conference, pp.1-8, 2007. ,
Cryptonite ??? A Programmable Crypto Processor Architecture for High-Bandwidth Applications, Organic and Pervasive Computing?ARCS 2004, pp.184-198, 2004. ,
DOI : 10.1007/978-3-540-24714-2_15
Architectural support for fast symmetrickey cryptography, ACM SIGARCH Computer Architecture News, vol.28, issue.5, pp.178-189, 2000. ,
A configurable AES processor for enhanced security, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, pp.361-366, 2005. ,
A Secure Self-Reconfiguring Architecture Based on Open-Source Hardware, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05), pp.7-10, 2006. ,
DOI : 10.1109/RECONFIG.2005.7
Reconfigurable Cryptographic Processor, proceeding of the Workshop on Circuits, Systems and Signal Processing, 2006. ,
A multiplatform controller allowing for maximum Dynamic Partial Reconfiguration throughput, pp.535-538, 2008. ,
Very Compact FPGA Implementations of the AES Algorithm Why Yet Another AES Implementation Very Compact FPGA Implementation of the AES Algorithm, Cryptographic Hardware and Embedded Systems -CHES 2003, pp.319-333, 2003. ,
A Study of Non-Blocking Switching Networks, Bell System Technical Journal, vol.32, issue.2, pp.406-424, 1953. ,
DOI : 10.1002/j.1538-7305.1953.tb01433.x
Architectural overview of the SPEAKeasy system, IEEE Journal on Selected Areas in Communications, vol.17, issue.4, pp.650-661, 1999. ,
A taxonomy for congestion control algorithms in packet switching networks An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.34-45, 1995. ,
Instruction-level distributed processing for symmetrickey cryptography, Proceedings International Parallel and Distributed Processing Symposium, p.10, 2003. ,
USRP TM Family Products and Daughter Boards, 2011. ,
A QdS-enabled packet scheduling algorithm for IPSec multi-accelerator based systems, p.221, 2005. ,
Weaknesses in the Key Scheduling Algorithm of RC4, proceedings of the 8th Annual International Workshop on Selected Areas in Cryptography, pp.1-24, 2001. ,
Celator: A Multi-algorithm Cryptographic Coprocessor, Proc. International Conference on Reconfigurable Computing and FPGAs ReConFig '08, pp.438-443, 2008. ,
An Overview of Reconfigurable Hardware in Embedded Systems, EURASIP Journal on Embedded Systems, vol.20, issue.2, pp.1-19, 2006. ,
DOI : 10.1109/TC.2003.1234532
Open-source SCA-based core framework and rapid development tools enable software-defined radio education and research, IEEE Communications Magazine, vol.47, issue.10, pp.48-55, 2009. ,
DOI : 10.1109/MCOM.2009.5273808
HCrypt: A Novel Concept of Crypto-processor with Secured Key Management, 2010 International Conference on Reconfigurable Computing and FPGAs, pp.280-285, 2010. ,
DOI : 10.1109/ReConFig.2010.38
URL : https://hal.archives-ouvertes.fr/hal-00750348
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs, 2010 International Conference on Field Programmable Logic and Applications, pp.414-421, 2010. ,
DOI : 10.1109/FPL.2010.86
Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011. ,
DOI : 10.1109/DTIS.2011.5941419
URL : https://hal.archives-ouvertes.fr/hal-00579020
Secure extension of softcore genralpurpose processors for symmetric key cryptography, 6th international Workshop on Reconfigurable Communication Centric Systems on Chip, 2011. ,
Network Processors, Systems on, p.722, 2008. ,
Reconfigurable Security Support for Embedded Systems, System Sciences HICSS '06. Proceedings of the 39th Annual Hawaii International Conference on, pp.250-250, 2006. ,
A Sound Method for Switching between Boolean and Arithmetic Masking, Cryptographic Hardware and Embedded Systems ? CHES 2001, pp.3-15, 2001. ,
A reconfigurable crypto sub system for the software communication architecture, Military Communications Conference, 2009. ,
Partial Reconfiguration Bitstream Compression for Virtex FPGAs, pp.183-185, 2008. ,
Intel Advanced Encryption Standard (AES) Instructions Set, Intel Mobility Group, pp.1-79, 2010. ,
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems, 2007 IEEE Symposium on Security and Privacy (SP '07), pp.281-295, 2007. ,
DOI : 10.1109/SP.2007.28
Real-time configuration code decompression for dynamic FPGA self-reconfiguration, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., pp.138-143, 2004. ,
DOI : 10.1109/IPDPS.2004.1303113
Sierra II Datasheet, Harris Corp, 2005. ,
Fault tolerant ICAP controller for highreliable internal scrubbing, Aerospace Conference, pp.1-10, 2008. ,
Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors, IEEE Transactions on Computers, vol.55, pp.366-372, 2006. ,
Service disciplines for guaranteed performance service in packetswitching networks Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks, Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.1374-1396, 1995. ,
Specifications G.711 ,
Specification G.729 ,
Advances in Cryptology - EUROCRYPT, pp.443-461, 2009. ,
The flow of software defined radio waveform development based on SCARI, 5th International Conference on Wireless Communications, Networking and Mobile Computing, pp.1-4, 2009. ,
The SOC design of a highly secure and reliable storage using a conceptual environment, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.865-868, 2004. ,
Software Communications Architecture Specification, no. 2.2.2. JTRS, 2006. ,
Modem Hardware Abstraction Layer Application Program Interface, 2007. ,
Software communications architecture specification, Next Version, 2010. ,
SeReCon: A Secure Dynamic Partial Reconfiguration Controller, 2008 IEEE Computer Society Annual Symposium on VLSI, pp.292-297, 2008. ,
DOI : 10.1109/ISVLSI.2008.61
SRAM-FPGA implementation of masked S- Box based DPA countermeasure for AES, pp.74-77, 2008. ,
Pipelined memory shared buffer for VLSI switches, ACM SIGCOMM Computer Communication Review, vol.25, issue.4, pp.39-48, 1995. ,
PicoBlaze User Resources, Xilinx ,
La cryptographie militaire, Journal des sciences militaires, vol.IX, pp.5-38, 1883. ,
An SCA security supplement compliant radio architecture, Proc. IEEE Military Communications Conference MILCOM 2005, pp.2244-2250, 2005. ,
Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1587-1592, 2007. ,
DOI : 10.1109/DATE.2007.364528
URL : https://hal.archives-ouvertes.fr/hal-00156590
Run-time Partial Reconfiguration speed investigation and architectural design space exploration, pp.498-502, 2009. ,
Run-time Partial Reconfiguration speed investigation and architectural design space exploration, Proc. Int. Conf. Field Programmable Logic and, pp.498-502, 2009. ,
Run-time Partial Reconfiguration speed investigation and architectural design space exploration, pp.498-502, 2009. ,
Multi-gigabit GCM-AES Architecture Optimized for FPGAs, CHES '07: Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems, pp.227-238, 2007. ,
DOI : 10.1007/978-3-540-74735-2_16
The price of security in wireless sensor networks, Computer Networks, vol.54, issue.17, pp.2967-2978, 2010. ,
An FPGA Implementation of CCM Mode Using AES, Information Security and Cryptology- ICISC 2005, pp.322-334, 2006. ,
CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor, Cryptographic Hardware and Embedded Systems, p.726, 1999. ,
DOI : 10.1007/3-540-48059-5_21
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.41.85
Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture, Proceedings of the conference on Design, automation and test in Europe (DATE), pp.355-360, 2007. ,
Development Approaches for an International Tactical Radio Cryptographic API, Proceedings of the SDR'08 Technical Conference and Product Exposition, 2008. ,
FPGA-based single chip cryptographic solution Military Embedded Systems, 2007. ,
A man-in-the-middle attack on UMTS, Proceedings of the 2004 ACM workshop on Wireless security -WiSe '04, p.90, 2004. ,
A taxonomy of DDoS attack and DDoS defense mechanisms, ACM SIGCOMM Computer Communication Review, vol.34, issue.2, p.39, 2004. ,
The software radio architecture, IEEE Communications Magazine, vol.33, issue.5, pp.26-38, 1995. ,
A HIGH ASSURANCE WIRELESS COMPUTING SYSTEM (HAWCS) FOR SOFTWARE DEFINED RADIO, Proceeding of the SDR 06 Technical Conference and Product Expositi, 2006. ,
A Self-Routing Benes Network and Parallel Permutation Algorithms, IEEE Transactions on Computers, vol.30, issue.5, pp.332-340, 1981. ,
FIPS-197, Nist, 2001. ,
Special Publication 800-38A, Nist, 2001. ,
Special Publication 800-38D, NIST, 2007. ,
Vectorized AES Core for High-throughput Secure Environments, High Performance Computing for Computational Science -VECPAR 2008 ,
DOI : 10.1007/978-3-540-92859-1_10
Branch target buffer design and optimization, IEEE Transactions on Computers, vol.42, issue.4, pp.396-412, 1993. ,
Spread spectrum for mobile communications, IEEE Transactions on Vehicular Technology, vol.40, issue.2, pp.313-322, 1991. ,
A Disruptive Receiver Architecture Dedicated to Software-Defined Radio, Proceedings of the 39th conference on Design automation -DAC '02, pp.344-348, 2002. ,
DOI : 10.1109/TCSII.2008.919512
URL : https://hal.archives-ouvertes.fr/hal-00274011
Stratified round Robin: a low complexity packet scheduler with bandwidth fairness and bounded delay, Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications -SIGCOMM '03, p.239, 2003. ,
Impact of Encryption on QdS in Voip, 2010 IEEE Second International Conference on Social Computing, pp.721-726, 2010. ,
Cornfield Multi-Chip Module ,
Two-dimensional Benes network, Proceedings. The Twenty-Second Southeastern Symposium on System Theory, pp.614-619, 1990. ,
Superscalar Coprocessor for High-Speed Curve-Based Cryptography, pp.415-429, 2006. ,
DOI : 10.1007/11894063_33
Domain-specific codesign for embedded security, Computer, vol.36, issue.4, pp.68-74, 2003. ,
Proposal and evaluation of security schemes for software-defined radio, 14th IEEE Proceedings on Personal, Indoor and Mobile Radio Communications, pp.114-118, 2003. ,
A Revised Secure Authentication Protocol for IEEE 802, 2010 International Conference on Advances in Computer Engineering, pp.34-38, 2010. ,
Local heating attacks on Flash memory devices, IEEE, 2009. ,
A key recovery attack on the 802.11b wired equivalent privacy protocol (WEP), ACM Transactions on Information and System Security, vol.7, issue.2, pp.319-332, 2004. ,
Introduction to Side-Channel Attacks, Secure Integrated Circuits and Systems, I. M. R. Verbauwhede, pp.27-42, 2010. ,
Fuzzing: Brute Force Vulnerability Discovery, 2007. ,
Threat Analysis of GNU Software Radio, 2005. ,
End-to-End QdS Network Design: Quality of Service in LANs, WANs, and VPNs (Networking Technology), 2004. ,
TPM Main Specification Version 1.1b, 2003. ,
Practical attacks against WEP and WPA, p.79, 2009. ,
CCproc: An Efficient Cryptographic Coprocessor, proceedings of 16th IFIP/IEEE International Conference on Very Large Scale Integration, pp.160-163, 2008. ,
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers, Reconfigurable Computing: Architectures, Tools and Applications, pp.318-323, 2009. ,
An instruction set extension for fast and memory-efficient AES implementation Lecture notes in computer science, pp.11-21 ,
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors, Cryptographic Hardware and Embedded Systems -CHES 2006, pp.270-284, 2006. ,
Boosting AES Performance on a Tiny Processor Core, Topics in Cryptology ? CT-RSA 2008, pp.170-186, 2008. ,
Multi Fault Laser Attacks on Protected CRT-RSA, pp.75-86, 2010. ,
The Rise of Reconfigurable Systems SOFTWARE DEFINED RADIO SOLUTIONS Experience making JTRS work, from the SCA, to Waveforms, to Secure Radios, proceedings of Engineering of Reconfigurable Systems and Application conference Proceeding of the SDR 05 Technical Conference and Product Exposition, 2003. ,
Secure download system based on software defined radio composed of FPGAs, pp.437-441 ,
The MOLEN polymorphic processor, IEEE Transactions on Computers, vol.53, issue.11, pp.1363-1375, 2004. ,
Application specific architectures, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '01, p.181, 2001. ,
DOI : 10.1145/502217.502247
Single- and Multi-core Configurable AES Architectures for Flexible Security, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.541-552, 2010. ,
DOI : 10.1109/TVLSI.2009.2013231
Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defenses, Cryptographic Hardware and Embedded Systems ? CHES 2000, pp.45-68, 2000. ,
Counter with CBC-MAC (CCM), Submission to NIST, 2002. ,
Security on FPGAs, ACM Transactions on Embedded Computing Systems, vol.3, issue.3, pp.534-574, 2004. ,
DOI : 10.1145/1015047.1015052
Packet scheduling for QdS support in IEEE 802.16 broadband wireless access systems, International Journal of Communication Systems, vol.16, issue.1, pp.81-96, 2003. ,
How Secure Are FPGAs in Cryptographic Applications?, Field Programmable Logic and Application, pp.91-100, 2003. ,
CryptoManiac: a fast flexible architecture for secure communication, 28th Annual International Symposium on Computer Architecture, pp.110-119, 2001. ,
CryptoBlaze: 8-bit Security Microcontroller (XAPP374), 2003. ,
UG360: Virtex-6 FPGA Configuration, 2010. ,
UG702: Partial Reconfiguration User Guide, 2011. ,
On the Price of Security in Large-Scale Wireless Ad Hoc Networks, IEEE/ACM Transactions on Networking, vol.19, issue.2, pp.319-332, 2011. ,
DOI : 10.1109/TNET.2011.2106162
Secure partial reconfiguration of {FPGAs}, 2005. ,