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Limites de l'intégration des masques de gravure et d'un matériau diélectrique hybride pour la fabrication des interconnexions en microélectronique

Abstract : From 45 nm technological node, metallic interconnect lines of microelectronic circuits are isolated by low-k materials (porous SiOCH). These porous materials are sensitive to fabrication processes and their degradation must be minimized to keep good electrical and mechanical performances. Moreover, the dimension shrinkage of metallic lines leads to an increase of copper resistivity. To limit it, works are performed on the metallurgy and on the control of line roughness of copper. This work focuses on two limits encountered during fabrication of interconnects: on one hand during pattern transfer by plasma etching from a metallic or organic mask into SiOCH materials, and one the other hand during SiOCH hybrid material integration, made porous after the etching or metallization of trenches steps. Particularly, it is pointed out that etching masks can lead to profile distortions due to the effect of mechanical stress relaxation for metallic masks or modification of their composition for organic masks. A preliminary study of line width roughness transfer during etching, with CD-AFM measurements, is presented. The interest of SiOCH hybrid material integration to solve some problematics of porous SiOCH degradation induced by fabrication processes is demonstrated.
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Submitted on : Thursday, February 9, 2012 - 1:31:23 PM
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Julien Ducote. Limites de l'intégration des masques de gravure et d'un matériau diélectrique hybride pour la fabrication des interconnexions en microélectronique. Micro et nanotechnologies/Microélectronique. Université de Grenoble, 2010. Français. ⟨tel-00668087⟩

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