Abstract : Rising design complexities and high manufacturing costs of System on Chip (SoCs) in deep submicron nodes (beyond 90nm) have reached levels where dedicated SoCs can no longer be designed for every application. They must have some post manufacturing flexibility to amortize the high development costs to several end markets. The Field Programmable Gate Arrays (FPGAs) are well known for their flexibility and ease of design modification. With the continuous architectural innovations and Moore's law they have become programmable platforms and in many cases provide a good alternative to implement SoCs directly on them. Unfortunately FPGAs suffer from large silicon gap compared to ASICs/ASSPs. This restricts their use in many high volume applications, and despite enormous benefits of flexibility FPGAs still represent a small niche in industry from revenues stand point compared to ASICs/ASSPs. An obvious choice that comes in mind in such scenario is embedded FPGAs (eFPGAs) to bring benefits of FPGAs right inside SoCs, bridging their challenges for flexibility, product differentiation, time to market etc. However concept of eFPGAs is not new to industry and is historically well known for never succeeding, despite undeniable benefits and potentials. The thesis extensively revolves around embedded FPGAs (eFPGAs). It conducts detailed survey focused on programmable technologies to investigate potentials and challenges of eFPGAs and probable failure reasons of several past attempts of different kinds. Based on survey knowledge, technology independent soft eFPGAs of FPGA-like mesh-based classical architecture with standard RTL programming flow are investigated. Detailed eFPGA architectural explorations (including CAD tools) are conducted to explore silicon-efficient (logic density, power, performance etc.) eFPGA architectures. Among notable innovations achieved is unified switch block with complete removal of connection block and local interconnect of classical mesh-based FPGAs (VPR-like) while maintaining good routing efficiency. All experiments are conducted on 65nm CMOS low power STMicroelectronics process to get practical silicon values and perspectives. Finally eFPGAs in systems (SoCs) potentials and challenges are addressed. A reconfigurable acceleration scenario with ESL exploitation (for programming ease) and full silicon tradeoffs visualization is presented with integration of eFPGA with LEON3 processor (as a functional and co-processor unit, with also highlighting potential flaws of functional unit in industrial perspectives). An interesting case study for perspectives of emerging MRAM memories for eFPGAs is also presented.