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W. Zhu, V. C. Sreedhar, Z. Hu, and G. R. Gao, Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures, ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, pp.35-45, 2007.

Y. Zhu and F. Mueller, Exploiting synchronous and asynchronous DVS for feedback EDF scheduling on an embedded platform, ACM Transactions on Embedded Computing Systems, vol.7, issue.1, pp.1-26, 2007.
DOI : 10.1145/1324969.1324972

A. Abdallah, A. Gamatié, and J. Dekeyser, Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, Technique et science informatiques (TSI), 2010.
DOI : 10.3166/tsi.30.1089-1113

A. Abdallah, A. Gamatié, and J. Dekeyser, Correct and energy-efficient design of SoCs: The H.264 encoder case study, 2010 International Symposium on System on Chip, 2010.
DOI : 10.1109/ISSOC.2010.5625558
URL : https://hal.archives-ouvertes.fr/inria-00522792

A. Abdallah, High-Level SoC Specification Towards a Design Space Exploration : Downscaler Case Study, EuroDocInfo10, 2010.

A. Abdallah, A. Gamatié, and J. Dekeyser, Model-Driven Design of Embedded Multimedia Applications on SoCs, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009.
DOI : 10.1109/DSD.2009.171

A. Abdallah, A. Gamatié, and J. Dekeyser, MARTE-based design of a multimedia application and formal analysis, 2008 Forum on Specification, Verification and Design Languages, 2008.
DOI : 10.1109/FDL.2008.4641439
URL : https://hal.archives-ouvertes.fr/inria-00567972

A. Abdallah, A. Gamatié, and J. Dekeyser, Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, Symposium en Architecture de Machines (SYMPA'13), 2009.