Conception de SoC à Base d'Horloges Abstraites : Vers l'Exploration d'Architectures en MARTE

Adolf Samir Abdallah 1
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, INRIA Lille - Nord Europe
Abstract : Modern high-performance embedded applications as found in multimedia, biomedical signal processing or biometric data processing are increasingly complex and resource-demanding. The quest for the ultimate execution performance on single processor chips is unfortunately a deadend. Instead, the promising solution is Multi-Processor System-on-Chip (MPSoC). However, the design of MPSoCs for high-performance embedded applications is a very difficult task due to a number of crucial constraints to meet: functionality correctness, temporal performance, energy efficiency and optimized memory size. Among the necessary ingredients for a successful design, we mention first the need of expressive enough programming models for describing the potential parallelism inherent to target applications. Second, we need ways avoiding tedious explorations of best architecture configurations for system execution (e.g. processors type and frequency, memory footprint), especially for complex data-intensive applications mapped on massively parallel architectures. Third, several abstraction levels must be taken into account to better address design complexity. Considering a single simulation level at which all implementation details are considered yields very accurate results, but is more time consuming and tedious, even sometimes impossible due to system complexity. For this reason, starting the design process at a high abstraction level, where only key information about the system are described makes it easier to take early decisions about the configuration choices at a very low cost. In order to deal with the above challenges concerning the design of high-performance applications on MPSoCs, we propose in this thesis to use the MARTE/UML profile for the modeling of system functionality, execution architectures and allocation of both parts. The MARTE profile is expressive enough to describe high performance applications (e.g. RSM and GCM packages and the CCSL language) and MPSoC architectures (e.g. HRM package). For the verification of the system and the design space exploration, we define an abstraction of the resulting model with abstract clocks, inspired by those of synchronous reactive languages. The traces associated with such clocks capture the behavior of a system by representing the activity of processing units, i.e. processors, when achieving functionality. An analysis technique, also inspired by the synchronous approach, is also defined. It enables to verify functional constraints: data dependencies induced by a MARTE model, activation rate constraints between components. In addition, it allows us to deal with non functional properties: execution time, deadline preservation, energy consumption. These properties are directly related to the number of processors involved in system execution as well as their associated frequency values. From an overall viewpoint, the main contribution of this thesis is the definition an abstract clock-based framework that aims to facilitate MPSoC design space exploration at a high abstraction level. It has been made concrete within an environment, referred to as GASPARD, dedicated to the codesign of high-performance embedded systems. Our solution is validated on a case study consisting of a JPEG encoder, with very promising results.
Document type :
Modeling and Simulation. Université des Sciences et Technologie de Lille - Lille I, 2011. French
Contributor : Adolf Abdallah <>
Submitted on : Monday, May 30, 2011 - 11:19:26 PM
Last modification on : Tuesday, May 31, 2011 - 9:11:18 AM


  • HAL Id : tel-00597031, version 1



Adolf Samir Abdallah. Conception de SoC à Base d'Horloges Abstraites : Vers l'Exploration d'Architectures en MARTE. Modeling and Simulation. Université des Sciences et Technologie de Lille - Lille I, 2011. French. <tel-00597031>




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