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F. Abouzeid, S. Clerc, F. Firmin, M. Renaudin, and G. Sicard, A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications, Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, ISLPED '09, p.225230, 2009.
DOI : 10.1145/1594233.1594288
URL : https://hal.archives-ouvertes.fr/hal-00421662

G. Roche and . Sicard, A 40nm cmos, 1.27nj, 330mv, 600khz, bose chaudhuri hocquenghem 252 bits frame decoder, ICICDT. IEEE, pp.78-81, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00569011

F. Abouzeid, S. Clerc, F. Firmin, M. Renaudin, and G. Sicard, 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications, TODAES. ACM, pp.2010-145
DOI : 10.1145/1970353.1970369
URL : https://hal.archives-ouvertes.fr/hal-00672355

B. De-l-'auteur-brevets, S. Clerc, J. Schoelkopff, F. Firmin, and F. Abouzeid, Single phase clock and low power dynamic flip-flop, 2009.

F. Abouzeid, F. Firmin, and S. Clerc, Method of electronic logic synthesis, 2010.

F. Abouzeid and S. Clerc, Ultra-low voltage 10t sram

F. Abouzeid, S. Clerc, P. Roche, and D. Auteur, Boost circuit for memory device, p.146, 2010.