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Etude d'architecture et circuiterie digitale dans le régime sous-le-seuil en technologie submicronique

Abstract : Ultra-low voltage enables to answer the limitations of the wearable mobile applications with an energy efficiency improved by a factor x10, at the price of an increased transistor variability limiting the predictability of the results. In respect with the industrial requirements, this thesis presents the development of logical cells optimized at ultra-low voltage, using a technology independent methodology. These cells, certified then validated by silicon measurements in 40nm, led to the design of a digital circuit, fabricated on silicon, which analysis highlighted the adaptations needed to enhance the yield and the predictability of the results. At last, a memory cell was developed and optimized at ultra-low voltage. Read and write assist solutions were conceived in order to reinforce the tolerance to variability. A 128kb memory demonstrator was then fabricated in 65nm to validate these developments.
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https://tel.archives-ouvertes.fr/tel-00591527
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Submitted on : Monday, May 9, 2011 - 3:09:19 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, March 30, 2017 - 10:13:17 AM

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  • HAL Id : tel-00591527, version 1

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CNRS | TIMA | UGA

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F. Abouzeid. Etude d'architecture et circuiterie digitale dans le régime sous-le-seuil en technologie submicronique. Micro et nanotechnologies/Microélectronique. Université de Grenoble, 2010. Français. ⟨tel-00591527⟩

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